quartus-clock.RAR - 源码下载|嵌入式/单片机编程|VHDL编程|源代码

设计FPGA电路以模拟多功能电子表的工作过程，功能如下：（1 ）数字钟，要求从00：00 ：00点计到23 ：59：59 （2）数字跑表（3 ）调整时间 (4)闹钟设置，可以设置2个闹钟，闹钟时间到了后会提醒，提醒时间持续20 秒，如果此时按A键，则该闹钟解除提醒，如果按住B键，闹钟暂停提醒。但是3 分钟后重复提醒一次。如果闹钟响时没有按键，则响完20秒之后暂停，然后同样3 分钟后重新提醒一次。（5 ）日期设置。可以设置当前的日期，

比如2012年08月20 日。-Design FPGA circuits to analog the multifunctional electronic table work process, the following functions: (1) digital clock count: 00 points from 00:00 to 23: 59:59 (2) digital the stopwatch (3) to adjust the time (4 ) set the alarm clock, can set two alarm clock, alarm time to remind reminder time for 20 seconds, then press the A key, the alarm clock lifted reminder, if you hold down the B button, snooze alert. But three minutes later repeated reminder. If the alarm goes off, no buttons, sound finished 20 seconds after the pause, and then the same three minutes after the re-remind once. (5) The date is set. Can be set to the current date, such as the August 20, 2012.

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下载文件列表

final\db\prev_cmp_state_ctr.asm.qmsg

.....\..\prev_cmp_state_ctr.fit.qmsg

.....\..\prev_cmp_state_ctr.map.qmsg

.....\..\prev_cmp_state_ctr.qmsg

.....\..\prev_cmp_state_ctr.tan.qmsg

.....\..\prev_cmp_test.asm.qmsg

.....\..\prev_cmp_test.fit.qmsg

.....\..\prev_cmp_test.map.qmsg

.....\..\prev_cmp_test.qmsg

.....\..\prev_cmp_test.sim.qmsg

.....\..\prev_cmp_test.tan.qmsg

.....\..\state_ctr.asm.qmsg

.....\..\state_ctr.asm_labs.ddb

.....\..\state_ctr.cbx.xml

.....\..\state_ctr.cmp.bpm

.....\..\state_ctr.cmp.cdb

.....\..\state_ctr.cmp.ecobp

.....\..\state_ctr.cmp.hdb

.....\..\state_ctr.cmp.logdb

.....\..\state_ctr.cmp.rdb

.....\..\state_ctr.cmp.tdb

.....\..\state_ctr.cmp0.ddb

.....\..\state_ctr.cmp_bb.cdb

.....\..\state_ctr.cmp_bb.hdb

.....\..\state_ctr.cmp_bb.logdb

.....\..\state_ctr.cmp_bb.rcf

.....\..\state_ctr.dbp

.....\..\state_ctr.db_info

.....\..\state_ctr.eco.cdb

.....\..\state_ctr.eds_overflow

.....\..\state_ctr.fit.qmsg

.....\..\state_ctr.fnsim.cdb

.....\..\state_ctr.fnsim.hdb

.....\..\state_ctr.fnsim.qmsg

.....\..\state_ctr.hier_info

.....\..\state_ctr.hif

.....\..\state_ctr.map.bpm

.....\..\state_ctr.map.cdb

.....\..\state_ctr.map.ecobp

.....\..\state_ctr.map.hdb

.....\..\state_ctr.map.logdb

.....\..\state_ctr.map.qmsg

.....\..\state_ctr.map_bb.cdb

.....\..\state_ctr.map_bb.hdb

.....\..\state_ctr.map_bb.logdb

.....\..\state_ctr.pre_map.cdb

.....\..\state_ctr.pre_map.hdb

.....\..\state_ctr.psp

.....\..\state_ctr.pss

.....\..\state_ctr.rtlv.hdb

.....\..\state_ctr.rtlv_sg.cdb

.....\..\state_ctr.rtlv_sg_swap.cdb

.....\..\state_ctr.sgdiff.cdb

.....\..\state_ctr.sgdiff.hdb

.....\..\state_ctr.signalprobe.cdb

.....\..\state_ctr.sim.cvwf

.....\..\state_ctr.sim.hdb

.....\..\state_ctr.sim.qmsg

.....\..\state_ctr.sim.rdb

.....\..\state_ctr.simfam

.....\..\state_ctr.sld_design_entry.sci

.....\..\state_ctr.sld_design_entry_dsc.sci

.....\..\state_ctr.smp_dump.txt

.....\..\state_ctr.syn_hier_info

.....\..\state_ctr.tan.qmsg

.....\..\state_ctr.tis_db_list.ddb

.....\..\test.asm.qmsg

.....\..\test.asm_labs.ddb

.....\..\test.cbx.xml

.....\..\test.cmp.bpm

.....\..\test.cmp.cdb

.....\..\test.cmp.ecobp

.....\..\test.cmp.hdb

.....\..\test.cmp.logdb

.....\..\test.cmp.rdb

.....\..\test.cmp.tdb

.....\..\test.cmp0.ddb

.....\..\test.cmp_bb.cdb

.....\..\test.cmp_bb.hdb

.....\..\test.cmp_bb.logdb

.....\..\test.cmp_bb.rcf

.....\..\test.dbp

.....\..\test.db_info

.....\..\test.eco.cdb

.....\..\test.eds_overflow

.....\..\test.fit.qmsg

.....\..\test.fnsim.hdb

.....\..\test.fnsim.qmsg

.....\..\test.hier_info

.....\..\test.hif

.....\..\test.map.bpm

.....\..\test.map.cdb

.....\..\test.map.ecobp

.....\..\test.map.hdb

.....\..\test.map.logdb

.....\..\test.map.qmsg

.....\..\test.map_bb.cdb

.....\..\test.map_bb.hdb

.....\..\test.map_bb.logdb

.....\..\test.pre_map.cdb

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