文件名称:VHDL
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电路主要由七个模块组成:时钟产生模块用于产生1KHz的扫描时钟和1Hz的时钟;二分频模块用于对1Hz的时钟信号二分频;测量/校验选择模块用于功能选择;计数模块用于对输入的cp信号计数;送存选择、报警电路根据选择的量程送存信号并显示单位,在超出所选量程时报警;锁存器锁存要显示的结果;扫描显示模块在1KHz的扫描时钟下,依次扫描三个数码管,并显示结果。-The circuit consists of seven main modules: clock generation module is used to generate 1KHz scan clock and 1Hz clock frequency module for 1Hz clock signal frequency measurement/calibration selection module for function selection count module for the input the cp signal count deposit options, alarm deposit signal circuit according to the selected range and display units, within the selected range alarm latch latches to be displayed scanning display module at 1KHz the scan clock, scan the three digits, and displays the results.
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VHDL.txt