文件名称:ethernet__verilog
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fpga模拟以太网物理层的源代码，用verilog硬件描述语言开发。
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下载文件列表
压缩包 : 111186775ethernet__verilog.rar 列表 ethernet__verilog\bench\CVS\Entries ethernet__verilog\bench\CVS\Repository ethernet__verilog\bench\CVS\Root ethernet__verilog\bench\verilog\CVS\Entries ethernet__verilog\bench\verilog\CVS\Repository ethernet__verilog\bench\verilog\CVS\Root ethernet__verilog\bench\verilog\tb_eth_top.v ethernet__verilog\CVS\Entries ethernet__verilog\CVS\Repository ethernet__verilog\CVS\Root ethernet__verilog\doc\CVS\Entries ethernet__verilog\doc\CVS\Repository ethernet__verilog\doc\CVS\Root ethernet__verilog\doc\ethernet_product_brief_OC_head.pdf ethernet__verilog\doc\eth_speci.pdf ethernet__verilog\doc\src\CVS\Entries ethernet__verilog\doc\src\CVS\Repository ethernet__verilog\doc\src\CVS\Root ethernet__verilog\doc\src\ethernet_product_brief.doc ethernet__verilog\doc\src\eth_speci.doc ethernet__verilog\rtl\CVS\Entries ethernet__verilog\rtl\CVS\Repository ethernet__verilog\rtl\CVS\Root ethernet__verilog\rtl\verilog\CVS\Entries ethernet__verilog\rtl\verilog\CVS\Repository ethernet__verilog\rtl\verilog\CVS\Root ethernet__verilog\rtl\verilog\eth_clockgen.v ethernet__verilog\rtl\verilog\eth_crc.v ethernet__verilog\rtl\verilog\eth_defines.v ethernet__verilog\rtl\verilog\eth_maccontrol.v ethernet__verilog\rtl\verilog\eth_macstatus.v ethernet__verilog\rtl\verilog\eth_miim.v ethernet__verilog\rtl\verilog\eth_outputcontrol.v ethernet__verilog\rtl\verilog\eth_random.v ethernet__verilog\rtl\verilog\eth_receivecontrol.v ethernet__verilog\rtl\verilog\eth_register.v ethernet__verilog\rtl\verilog\eth_registers.v ethernet__verilog\rtl\verilog\eth_rxcounters.v ethernet__verilog\rtl\verilog\eth_rxethmac.v ethernet__verilog\rtl\verilog\eth_rxstatem.v ethernet__verilog\rtl\verilog\eth_shiftreg.v ethernet__verilog\rtl\verilog\eth_sync_clk1_clk2.v ethernet__verilog\rtl\verilog\eth_top.v ethernet__verilog\rtl\verilog\eth_transmitcontrol.v ethernet__verilog\rtl\verilog\eth_txcounters.v ethernet__verilog\rtl\verilog\eth_txethmac.v ethernet__verilog\rtl\verilog\eth_txstatem.v ethernet__verilog\rtl\verilog\eth_wishbonedma.v ethernet__verilog\rtl\verilog\timescale.v ethernet__verilog\sim\CVS\Entries ethernet__verilog\sim\CVS\Repository ethernet__verilog\sim\CVS\Root ethernet__verilog\sim\rtl_sim\CVS\Entries ethernet__verilog\sim\rtl_sim\CVS\Repository ethernet__verilog\sim\rtl_sim\CVS\Root ethernet__verilog\sim\rtl_sim\ncsim_sim\CVS\Entries ethernet__verilog\sim\rtl_sim\ncsim_sim\CVS\Repository ethernet__verilog\sim\rtl_sim\ncsim_sim\CVS\Root ethernet__verilog\sim\rtl_sim\run\CVS\Entries ethernet__verilog\sim\rtl_sim\run\CVS\Repository ethernet__verilog\sim\rtl_sim\run\CVS\Root ethernet__verilog\sim\rtl_sim\run\top_modelsim.do ethernet__verilog\sim\rtl_sim\src\CVS\Entries ethernet__verilog\sim\rtl_sim\src\CVS\Repository ethernet__verilog\sim\rtl_sim\src\CVS\Root ethernet__verilog\sim\rtl_sim\ncsim_sim\CVS ethernet__verilog\sim\rtl_sim\run\CVS ethernet__verilog\sim\rtl_sim\src\CVS ethernet__verilog\bench\verilog\CVS ethernet__verilog\doc\src\CVS ethernet__verilog\rtl\verilog\CVS ethernet__verilog\sim\rtl_sim\CVS ethernet__verilog\sim\rtl_sim\ncsim_sim ethernet__verilog\sim\rtl_sim\run ethernet__verilog\sim\rtl_sim\src ethernet__verilog\bench\CVS ethernet__verilog\bench\verilog ethernet__verilog\doc\CVS ethernet__verilog\doc\src ethernet__verilog\rtl\CVS ethernet__verilog\rtl\verilog ethernet__verilog\sim\CVS ethernet__verilog\sim\rtl_sim ethernet__verilog\bench ethernet__verilog\CVS ethernet__verilog\doc ethernet__verilog\rtl ethernet__verilog\sim ethernet__verilog