verification\verilog_src\testbench\clkgen\clkgen.v

............\...........\.........\clkgen

............\...........\.........\.pu_bfm\cpu_bfm.v

............\...........\.........\cpu_bfm

............\...........\.........\ow_slave\cmd_ctrl.v

............\...........\.........\........\iox.v

............\...........\.........\........\ow_slave.v

............\...........\.........\ow_slave

............\...........\.........\scoreboard\scoreboard.v

............\...........\.........\scoreboard

............\...........\.........\tb_ds1wm\tb_ds1wm.v

............\...........\.........\........\tc_ds1wm.v

............\...........\.........\tb_ds1wm

............\...........\testbench

............\...........\....s\cmd_recognition\nc_rundir\cds.lib

............\...........\.....\...............\.........\design_verilog_src_files.lst

............\...........\.....\...............\.........\design_vhdl_src_files.lst

............\...........\.....\...............\.........\hdl.var

............\...........\.....\...............\.........\ncsim.key

............\...........\.....\...............\.........\probe.tcl

............\...........\.....\...............\.........\run.csh

............\...........\.....\...............\.........\tb_src_files.lst

............\...........\.....\...............\nc_rundir

............\...........\.....\...............\README

............\...........\.....\...............\stimulus.inc

............\...........\.....\cmd_recognition

............\...........\.....\multi_ow_network\nc_rundir\cds.lib

............\...........\.....\................\.........\design_verilog_src_files.lst

............\...........\.....\................\.........\design_vhdl_src_files.lst

............\...........\.....\................\.........\hdl.var

............\...........\.....\................\.........\ncsim.key

............\...........\.....\................\.........\probe.tcl

............\...........\.....\................\.........\run.csh

............\...........\.....\................\.........\tb_src_files.lst

............\...........\.....\................\nc_rundir

............\...........\.....\................\README

............\...........\.....\................\stimulus.inc

............\...........\.....\multi_ow_network

............\...........\.....\scratchpad_integrity\nc_rundir\cds.lib

............\...........\.....\....................\.........\design_verilog_src_files.lst

............\...........\.....\....................\.........\design_vhdl_src_files.lst

............\...........\.....\....................\.........\hdl.var

............\...........\.....\....................\.........\ncsim.key

............\...........\.....\....................\.........\probe.tcl

............\...........\.....\....................\.........\run.csh

............\...........\.....\....................\.........\tb_src_files.lst

............\...........\.....\....................\nc_rundir

............\...........\.....\....................\README

............\...........\.....\....................\stimulus.inc

............\...........\.....\scratchpad_integrity

............\...........\.....\.ingle_search_rom\nc_rundir\cds.lib

............\...........\.....\.................\.........\design_verilog_src_files.lst

............\...........\.....\.................\.........\design_vhdl_src_files.lst

............\...........\.....\.................\.........\hdl.var

............\...........\.....\.................\.........\ncsim.key

............\...........\.....\.................\.........\probe.tcl

............\...........\.....\.................\.........\run.csh

............\...........\.....\.................\.........\tb_src_files.lst

............\...........\.....\.................\nc_rundir

............\...........\.....\.................\README

............\...........\.....\.................\stimulus.inc

............\...........\.....\single_search_rom

............\...........\tests

............\verilog_src

verification

README

design\verilog_src\ds1wm\clk_prescaler.v

......\...........\.....\ds1wm.v

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