文件名称:Verilog
- 所属分类：
- VHDL编程
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 62kb
- 下载次数：
- 0次
- 提 供 者：
- wangx******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
是关于FPGA的一些基本的应用例程，代码是用verilog写的。-Basic routines on the FPGA, the code is written in verilog.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Verilog\ascii_bcd.v
.......\bcd_ascii.v
.......\buzz.v
.......\clock.v
.......\counter.v
.......\counter_core.v
.......\counter_sim.v
.......\delay_time.v
.......\divisor.v
.......\div_sim.v
.......\div_sim.v.bak
.......\ds_drv.v
.......\ds_drv_s.bdf
.......\ds_drv_s.v
.......\ds_sel.v
.......\fifo.v
.......\flash.v
.......\i2c.v
.......\io_tri_state.v
.......\kb2bcd.v
.......\kb_drv.v
.......\kb_drv_test.v
.......\key.v
.......\lcd1602_drv.v
.......\led_drv.v
.......\mseq.v
.......\msg_decode.v
.......\msg_decode_test.v
.......\msg_encode.v
.......\mt48lc4m32b2.v
.......\mt48lc4m32b2_test.v
.......\ps2_drv.v
.......\pwm.v
.......\pwm_counter.v
.......\s373.v
.......\s373.v.bak
.......\scan_ascii.v
.......\sdram.v
.......\sdram.v.bak
.......\sel8.v
.......\shifter.v
.......\spi.v
.......\timer.v
.......\uart_rx.v
.......\uart_tx.v
.......\usb.v
.......\vga_drv.v
.......\复件 sdram.v
Verilog
.......\bcd_ascii.v
.......\buzz.v
.......\clock.v
.......\counter.v
.......\counter_core.v
.......\counter_sim.v
.......\delay_time.v
.......\divisor.v
.......\div_sim.v
.......\div_sim.v.bak
.......\ds_drv.v
.......\ds_drv_s.bdf
.......\ds_drv_s.v
.......\ds_sel.v
.......\fifo.v
.......\flash.v
.......\i2c.v
.......\io_tri_state.v
.......\kb2bcd.v
.......\kb_drv.v
.......\kb_drv_test.v
.......\key.v
.......\lcd1602_drv.v
.......\led_drv.v
.......\mseq.v
.......\msg_decode.v
.......\msg_decode_test.v
.......\msg_encode.v
.......\mt48lc4m32b2.v
.......\mt48lc4m32b2_test.v
.......\ps2_drv.v
.......\pwm.v
.......\pwm_counter.v
.......\s373.v
.......\s373.v.bak
.......\scan_ascii.v
.......\sdram.v
.......\sdram.v.bak
.......\sel8.v
.......\shifter.v
.......\spi.v
.......\timer.v
.......\uart_rx.v
.......\uart_tx.v
.......\usb.v
.......\vga_drv.v
.......\复件 sdram.v
Verilog