文件名称:Vsteepper_motH

  • 所属分类:
  • Windows编程
  • 资源属性:
  • [WORD]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 1.14mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • cpdc****
  • 相关连接:
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  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

步进电机 VHDL 控制,整步 半半步 细分 actel FPGA使用

-VHDL control of stepper motor, whole step, half half step segments actel FPGA use
(系统自动生成,下载前可以参看下载内容)

下载文件列表

Vsteepper_motH\Application Note Disclaimer.doc

..............\stepper_ip\designer\impl1\designer.log

..............\..........\........\.....\designer_genhdl.log

..............\..........\........\.....\top_stepper_ip.adb

..............\..........\........\.....\...............dtf\verify.log

..............\..........\........\.....\top_stepper_ip.ide_des

..............\..........\........\.....\top_stepper_ip.stp

..............\..........\........\.....\top_stepper_ip.tcl

..............\..........\hdl\baud_clk_gen.v

..............\..........\...\clkdiv_20M_to_10M.v

..............\..........\...\clk_by_2.v

..............\..........\...\clk_gen.v

..............\..........\...\debounce.v

..............\..........\...\debounce_blk.v

..............\..........\...\divideby5.v

..............\..........\...\div_by_16.v

..............\..........\...\global.v

..............\..........\...\mux_hw_sw.v

..............\..........\...\PLL20_to_10.v

..............\..........\...\pwm_gen_stepper.v

..............\..........\...\recv_control.v

..............\..........\...\serial.v

..............\..........\...\stepper_clk_gen.v

..............\..........\...\stepper_ip.v

..............\..........\...\stepper_module.v

..............\..........\...\top_serial.v

..............\..........\...\top_stepper.v

..............\..........\...\top_stepper_ip.v

..............\..........\...\xmit_control.v

..............\..........\Readme_stepper_ip.txt

..............\..........\simulation\modelsim.ini

..............\..........\..........\modelsim.ini.sav

..............\..........\..........\modelsim.log

..............\..........\..........\postsynth\baud_clk_gen\verilog.psm

..............\..........\..........\.........\............\_primary.dat

..............\..........\..........\.........\............\_primary.dbs

..............\..........\..........\.........\............\_primary.vhd

..............\..........\..........\.........\clkdiv_20@m_to_10@m\verilog.psm

..............\..........\..........\.........\...................\_primary.dat

..............\..........\..........\.........\...................\_primary.dbs

..............\..........\..........\.........\...................\_primary.vhd

..............\..........\..........\.........\..._by_2\verilog.psm

..............\..........\..........\.........\........\_primary.dat

..............\..........\..........\.........\........\_primary.dbs

..............\..........\..........\.........\........\_primary.vhd

..............\..........\..........\.........\........_1\verilog.psm

..............\..........\..........\.........\..........\_primary.dat

..............\..........\..........\.........\..........\_primary.dbs

..............\..........\..........\.........\..........\_primary.vhd

..............\..........\..........\.........\..........0\verilog.psm

..............\..........\..........\.........\...........\_primary.dat

..............\..........\..........\.........\...........\_primary.dbs

..............\..........\..........\.........\...........\_primary.vhd

..............\..........\..........\.........\..........1\verilog.psm

..............\..........\..........\.........\...........\_primary.dat

..............\..........\..........\.........\...........\_primary.dbs

..............\..........\..........\.........\...........\_primary.vhd

..............\..........\..........\.........\..........2\verilog.psm

..............\..........\..........\.........\...........\_primary.dat

..............\..........\..........\.........\...........\_primary.dbs

..............\..........\..........\.........\...........\_primary.vhd

..............\..........\..........\.........\..........3\verilog.psm

..............\..........\..........\.........\...........\_primary.dat

..............\..........\..........\.........\...........\_primary.dbs

..............\..........\..........\.........\...........\_primary.vhd

..............\..........\..........\.........\..........4\verilog.psm

..............\..........\..........\.........\...........\_primary.dat

..............\..........\..........\.

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