文件名称:VFIFOzipe
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用verilog实现异步FIFO，代码中有两个模块，使用时时注意顶层模块和底层模块，用quartus2即可打开直接使用。
-Asynchronous FIFO, with verilog code has two modules, using the constant attention of top-level module and bottom module with quartus2 to open.
-Asynchronous FIFO, with verilog code has two modules, using the constant attention of top-level module and bottom module with quartus2 to open.
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下载文件列表
VFIFOzipe\async_cmp.v
.........\async_fifo.v
.........\dp_ram.v
.........\rptr_empty.v
.........\wptr_full.v
VFIFOzipe
.........\async_fifo.v
.........\dp_ram.v
.........\rptr_empty.v
.........\wptr_full.v
VFIFOzipe