文件名称:FPGA--AES-algorithm
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本文介绍了AES 数据加密结构, 以及相关的有限域的知识及简单运算, 提出了一种用FPGA 高速实现AES 算法的方案, 该方
案设计的加密模块支持AES 标准的三种密钥长度: 128,192,256, 支持ECB, CBC, CTR 三种工作模式, 即支持feedback 和non- feedback
两种模式, 最后给出了本设计的性能指标-This article describes the AES data encryption structure, as well as the limited domain knowledge and simple computing the program an FPGA high-speed AES algorithm, the encryption module of the program supports three key lengths for AES standard: 128,192,256, supports three operating modes ECB, CBC, CTR, which is to support two modes of feedback and non-feedback. Finally, the performance of the design
案设计的加密模块支持AES 标准的三种密钥长度: 128,192,256, 支持ECB, CBC, CTR 三种工作模式, 即支持feedback 和non- feedback
两种模式, 最后给出了本设计的性能指标-This article describes the AES data encryption structure, as well as the limited domain knowledge and simple computing the program an FPGA high-speed AES algorithm, the encryption module of the program supports three key lengths for AES standard: 128,192,256, supports three operating modes ECB, CBC, CTR, which is to support two modes of feedback and non-feedback. Finally, the performance of the design
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FPGA AES algorithm.pdf