文件名称:DE3_150_CLR
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CLR-HSMC,ALTERA高速接口HSMC的视频转接子板基于DE3_150的例程，能够用FPGA实现工业相机视频采集以及VGA输出。-CLR-HSMC of ALTERA high-speed interface the HSMC The video adapter daughter board-based DE3_150 routines, to FPGA industrial camera video capture and VGA output.
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下载文件列表
DE3_150_CLR
...........\.sopc_builder
...........\.............\filters.xml
...........\.............\install.ptf
...........\.............\install2.ptf
...........\.............\preferences.xml
...........\altera_avalon_half_rate_bridge.v
...........\altera_avalon_half_rate_bridge_constraints.sdc
...........\altmemphy-library
...........\.................\auk_ddr_hp_controller.ocp
...........\alt_ddrx_addr_cmd.v
...........\alt_ddrx_afi_block.v
...........\alt_ddrx_avalon_if.v
...........\alt_ddrx_bank_timer.v
...........\alt_ddrx_bank_timer_info.v
...........\alt_ddrx_bank_timer_wrapper.v
...........\alt_ddrx_bypass.v
...........\alt_ddrx_cache.v
...........\alt_ddrx_clock_and_reset.v
...........\alt_ddrx_cmd_gen.v
...........\alt_ddrx_cmd_queue.v
...........\alt_ddrx_controller.v
...........\alt_ddrx_csr.v
...........\alt_ddrx_ddr2_odt_gen.v
...........\alt_ddrx_ddr3_odt_gen.v
...........\alt_ddrx_decoder.v
...........\alt_ddrx_decoder_40.v
...........\alt_ddrx_decoder_72.v
...........\alt_ddrx_ecc.v
...........\alt_ddrx_encoder.v
...........\alt_ddrx_encoder_40.v
...........\alt_ddrx_encoder_72.v
...........\alt_ddrx_input_if.v
...........\alt_ddrx_odt_gen.v
...........\alt_ddrx_rank_monitor.v
...........\alt_ddrx_state_machine.v
...........\alt_ddrx_timing_param.v
...........\alt_ddrx_wdata_fifo.v
...........\alt_mem_phy_defines.v
...........\auk_ddr_hp_controller.ocp
...........\auk_ddr_hp_controller.vhd
...........\ddr2.html
...........\ddr2.ppf
...........\ddr2.qip
...........\ddr2.v
...........\ddr2_advisor.ipa
...........\ddr2_alt_ddrx_controller_wrapper.v
...........\ddr2_auk_ddr_hp_controller_wrapper.v
...........\ddr2_controller_phy.v
...........\ddr2_example_driver.v
...........\ddr2_example_top.sdc
...........\ddr2_example_top.v
...........\ddr2_example_top.v.tmp2
...........\ddr2_example_top_1.v
...........\ddr2_example_top_10.v
...........\ddr2_example_top_11.v
...........\ddr2_example_top_12.v
...........\ddr2_example_top_2.v
...........\ddr2_example_top_3.v
...........\ddr2_example_top_4.v
...........\ddr2_example_top_5.v
...........\ddr2_example_top_6.v
...........\ddr2_example_top_7.v
...........\ddr2_example_top_8.v
...........\ddr2_example_top_9.v
...........\ddr2_ex_lfsr8.v
...........\ddr2_full_mem_model.v
...........\ddr2_high_performance_controller-library
...........\........................................\auk_ddr_hp_controller.ocp
...........\ddr2_mem_model.v
...........\ddr2_phy.html
...........\ddr2_phy.qip
...........\ddr2_phy.v
...........\ddr2_phy_alt_mem_phy.v
...........\ddr2_phy_alt_mem_phy_pll.qip
...........\ddr2_phy_alt_mem_phy_pll.v
...........\ddr2_phy_alt_mem_phy_pll_bb.v
...........\ddr2_phy_alt_mem_phy_seq.vhd
...........\ddr2_phy_alt_mem_phy_seq_wrapper.v
...........\ddr2_phy_autodetectedpins.tcl
...........\ddr2_phy_ddr_pins.tcl
...........\ddr2_phy_ddr_timing.sdc
...........\ddr2_phy_ddr_timing.tcl
...........\ddr2_phy_report_timing.tcl
...........\ddr2_phy_report_timing_core.tcl
...........\ddr2_phy_summary.csv
...........\ddr2_pin_assignments.tcl
...........\DDR2_SODIMM_Read_Port.v
...........\DDR2_SODIMM_Read_Port_hw.tcl
...........\DDR2_SODIMM_Write_Port.v
...........\DDR2_SODIMM_Write_Port_hw.tcl
...........\DE3.htm
...........\DE3.qpf
...........\DE3.qws
...........\DE3_assignment_defaults.qdf
...........\DE3_CLR.cdf
...........\DE3_CLR.done
...........\DE3_CLR.dpf
...........\DE3_CLR.fit.smsg
...........\DE3_CLR.fit.summary
...........\.sopc_builder
...........\.............\filters.xml
...........\.............\install.ptf
...........\.............\install2.ptf
...........\.............\preferences.xml
...........\altera_avalon_half_rate_bridge.v
...........\altera_avalon_half_rate_bridge_constraints.sdc
...........\altmemphy-library
...........\.................\auk_ddr_hp_controller.ocp
...........\alt_ddrx_addr_cmd.v
...........\alt_ddrx_afi_block.v
...........\alt_ddrx_avalon_if.v
...........\alt_ddrx_bank_timer.v
...........\alt_ddrx_bank_timer_info.v
...........\alt_ddrx_bank_timer_wrapper.v
...........\alt_ddrx_bypass.v
...........\alt_ddrx_cache.v
...........\alt_ddrx_clock_and_reset.v
...........\alt_ddrx_cmd_gen.v
...........\alt_ddrx_cmd_queue.v
...........\alt_ddrx_controller.v
...........\alt_ddrx_csr.v
...........\alt_ddrx_ddr2_odt_gen.v
...........\alt_ddrx_ddr3_odt_gen.v
...........\alt_ddrx_decoder.v
...........\alt_ddrx_decoder_40.v
...........\alt_ddrx_decoder_72.v
...........\alt_ddrx_ecc.v
...........\alt_ddrx_encoder.v
...........\alt_ddrx_encoder_40.v
...........\alt_ddrx_encoder_72.v
...........\alt_ddrx_input_if.v
...........\alt_ddrx_odt_gen.v
...........\alt_ddrx_rank_monitor.v
...........\alt_ddrx_state_machine.v
...........\alt_ddrx_timing_param.v
...........\alt_ddrx_wdata_fifo.v
...........\alt_mem_phy_defines.v
...........\auk_ddr_hp_controller.ocp
...........\auk_ddr_hp_controller.vhd
...........\ddr2.html
...........\ddr2.ppf
...........\ddr2.qip
...........\ddr2.v
...........\ddr2_advisor.ipa
...........\ddr2_alt_ddrx_controller_wrapper.v
...........\ddr2_auk_ddr_hp_controller_wrapper.v
...........\ddr2_controller_phy.v
...........\ddr2_example_driver.v
...........\ddr2_example_top.sdc
...........\ddr2_example_top.v
...........\ddr2_example_top.v.tmp2
...........\ddr2_example_top_1.v
...........\ddr2_example_top_10.v
...........\ddr2_example_top_11.v
...........\ddr2_example_top_12.v
...........\ddr2_example_top_2.v
...........\ddr2_example_top_3.v
...........\ddr2_example_top_4.v
...........\ddr2_example_top_5.v
...........\ddr2_example_top_6.v
...........\ddr2_example_top_7.v
...........\ddr2_example_top_8.v
...........\ddr2_example_top_9.v
...........\ddr2_ex_lfsr8.v
...........\ddr2_full_mem_model.v
...........\ddr2_high_performance_controller-library
...........\........................................\auk_ddr_hp_controller.ocp
...........\ddr2_mem_model.v
...........\ddr2_phy.html
...........\ddr2_phy.qip
...........\ddr2_phy.v
...........\ddr2_phy_alt_mem_phy.v
...........\ddr2_phy_alt_mem_phy_pll.qip
...........\ddr2_phy_alt_mem_phy_pll.v
...........\ddr2_phy_alt_mem_phy_pll_bb.v
...........\ddr2_phy_alt_mem_phy_seq.vhd
...........\ddr2_phy_alt_mem_phy_seq_wrapper.v
...........\ddr2_phy_autodetectedpins.tcl
...........\ddr2_phy_ddr_pins.tcl
...........\ddr2_phy_ddr_timing.sdc
...........\ddr2_phy_ddr_timing.tcl
...........\ddr2_phy_report_timing.tcl
...........\ddr2_phy_report_timing_core.tcl
...........\ddr2_phy_summary.csv
...........\ddr2_pin_assignments.tcl
...........\DDR2_SODIMM_Read_Port.v
...........\DDR2_SODIMM_Read_Port_hw.tcl
...........\DDR2_SODIMM_Write_Port.v
...........\DDR2_SODIMM_Write_Port_hw.tcl
...........\DE3.htm
...........\DE3.qpf
...........\DE3.qws
...........\DE3_assignment_defaults.qdf
...........\DE3_CLR.cdf
...........\DE3_CLR.done
...........\DE3_CLR.dpf
...........\DE3_CLR.fit.smsg
...........\DE3_CLR.fit.summary