文件名称:Static-PLL
介绍说明－－下载内容均来自于网络，请自行研究使用
基于Actel开发平台的静态锁相环设计，verilog实现-Actel development platform based on the static PLL design, verilog realized
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Static PLL\Static PLL实验例程.pdf
..........\Static_PLL_lab.rar
..........\..c_PLL\designer\impl1\designer.log
..........\.......\........\.....\designer_gen_ba.log
..........\.......\........\.....\designer_synth_check.log
..........\.......\........\.....\flashpro.log
..........\.......\........\.....\PLL_top.adb
..........\.......\........\.....\........dtf\PLL_top\$$FlashPro_FPBBALTLPT1.L$$
..........\.......\........\.....\...........\.......\PLL_top.log
..........\.......\........\.....\...........\.......\PLL_top.pro
..........\.......\........\.....\...........\.......\projectData\PLL_top.stp
..........\.......\........\.....\...........\verify.log
..........\.......\........\.....\PLL_top.ide_des
..........\.......\........\.....\PLL_top.pdb
..........\.......\........\.....\PLL_top.pdb.depends
..........\.......\........\.....\PLL_top.stp
..........\.......\........\.....\PLL_top.tcl
..........\.......\........\.....\PLL_top_1.adb
..........\.......\........\.....\PLL_top_1.ide_des
..........\.......\........\.....\PLL_top_ba.sdf
..........\.......\........\.....\PLL_top_ba.v
..........\.......\........\.....\Static_PLL.ide_des
..........\.......\hdl\ctrl_PLL.v
..........\.......\...\hdlsynchk.tcl
..........\.......\...\PLL_top.v
..........\.......\simulation\meminit.dat
..........\.......\..........\modelsim.ini
..........\.......\..........\modelsim.ini.sav
..........\.......\..........\modelsim.log
..........\.......\..........\presynth\@p@l@l_top\verilog.psm
..........\.......\..........\........\..........\_primary.dat
..........\.......\..........\........\..........\_primary.vhd
..........\.......\..........\........\.static_@p@l@l\verilog.psm
..........\.......\..........\........\..............\_primary.dat
..........\.......\..........\........\..............\_primary.vhd
..........\.......\..........\........\ctrl_@p@l@l\verilog.psm
..........\.......\..........\........\...........\_primary.dat
..........\.......\..........\........\...........\_primary.vhd
..........\.......\..........\........\stimulus\verilog.psm
..........\.......\..........\........\........\_primary.dat
..........\.......\..........\........\........\_primary.vhd
..........\.......\..........\........\tb_clock_minmax\verilog.psm
..........\.......\..........\........\...............\_primary.dat
..........\.......\..........\........\...............\_primary.vhd
..........\.......\..........\........\.estbench\verilog.psm
..........\.......\..........\........\.........\_primary.dat
..........\.......\..........\........\.........\_primary.vhd
..........\.......\..........\........\_info
..........\.......\..........\run.do
..........\.......\..........\vsim.wlf
..........\.......\..........\wave.do
..........\.......\.martgen\smartgen.aws
..........\.......\........\Static_PLL\Static_PLL.cxf
..........\.......\........\..........\Static_PLL.gen
..........\.......\........\..........\Static_PLL.log
..........\.......\........\..........\Static_PLL.v
..........\.......\........\Static_PLL_work.ixf
..........\.......\Stc_PLL.prj
..........\.......\stimulus\BtimErrors.log
..........\.......\........\files_to_build.txt
..........\.......\........\PLL_top.dsk
..........\.......\........\PLL_top.hpj
..........\.......\........\PLL_top_tbench.bk
..........\.......\........\PLL_top_tbench.btim
..........\.......\........\PLL_top_tbench.v
..........\.......\........\waveperl.log
..........\.......\.ynthesis\.recordref
..........\.......\.........\dm\PLL_top_1.xdm
..........\.......\.........\identify.log
..........\.......\.........\PLL_top.areasrr
..........\.......\.........\PLL_top.edn
..........\.......\.........\PLL_top.fse
..........\.......\.........\PLL_top.htm
..........\.......\.........\PLL_top.map
..........\.......\.........\PLL_top.sap
..........\.......\.........\PLL_top.sdf
..........\.......\.........\PLL_top.srd
..........\.......\.........\PLL_top.srm
..........\.......\.........\PLL_top.srr
..........\.......\.........\PLL_top.srs
..........\.......\.........\PLL_top.tlg
..........\.......\.........\PLL_top_1.areasr
..........\Static_PLL_lab.rar
..........\..c_PLL\designer\impl1\designer.log
..........\.......\........\.....\designer_gen_ba.log
..........\.......\........\.....\designer_synth_check.log
..........\.......\........\.....\flashpro.log
..........\.......\........\.....\PLL_top.adb
..........\.......\........\.....\........dtf\PLL_top\$$FlashPro_FPBBALTLPT1.L$$
..........\.......\........\.....\...........\.......\PLL_top.log
..........\.......\........\.....\...........\.......\PLL_top.pro
..........\.......\........\.....\...........\.......\projectData\PLL_top.stp
..........\.......\........\.....\...........\verify.log
..........\.......\........\.....\PLL_top.ide_des
..........\.......\........\.....\PLL_top.pdb
..........\.......\........\.....\PLL_top.pdb.depends
..........\.......\........\.....\PLL_top.stp
..........\.......\........\.....\PLL_top.tcl
..........\.......\........\.....\PLL_top_1.adb
..........\.......\........\.....\PLL_top_1.ide_des
..........\.......\........\.....\PLL_top_ba.sdf
..........\.......\........\.....\PLL_top_ba.v
..........\.......\........\.....\Static_PLL.ide_des
..........\.......\hdl\ctrl_PLL.v
..........\.......\...\hdlsynchk.tcl
..........\.......\...\PLL_top.v
..........\.......\simulation\meminit.dat
..........\.......\..........\modelsim.ini
..........\.......\..........\modelsim.ini.sav
..........\.......\..........\modelsim.log
..........\.......\..........\presynth\@p@l@l_top\verilog.psm
..........\.......\..........\........\..........\_primary.dat
..........\.......\..........\........\..........\_primary.vhd
..........\.......\..........\........\.static_@p@l@l\verilog.psm
..........\.......\..........\........\..............\_primary.dat
..........\.......\..........\........\..............\_primary.vhd
..........\.......\..........\........\ctrl_@p@l@l\verilog.psm
..........\.......\..........\........\...........\_primary.dat
..........\.......\..........\........\...........\_primary.vhd
..........\.......\..........\........\stimulus\verilog.psm
..........\.......\..........\........\........\_primary.dat
..........\.......\..........\........\........\_primary.vhd
..........\.......\..........\........\tb_clock_minmax\verilog.psm
..........\.......\..........\........\...............\_primary.dat
..........\.......\..........\........\...............\_primary.vhd
..........\.......\..........\........\.estbench\verilog.psm
..........\.......\..........\........\.........\_primary.dat
..........\.......\..........\........\.........\_primary.vhd
..........\.......\..........\........\_info
..........\.......\..........\run.do
..........\.......\..........\vsim.wlf
..........\.......\..........\wave.do
..........\.......\.martgen\smartgen.aws
..........\.......\........\Static_PLL\Static_PLL.cxf
..........\.......\........\..........\Static_PLL.gen
..........\.......\........\..........\Static_PLL.log
..........\.......\........\..........\Static_PLL.v
..........\.......\........\Static_PLL_work.ixf
..........\.......\Stc_PLL.prj
..........\.......\stimulus\BtimErrors.log
..........\.......\........\files_to_build.txt
..........\.......\........\PLL_top.dsk
..........\.......\........\PLL_top.hpj
..........\.......\........\PLL_top_tbench.bk
..........\.......\........\PLL_top_tbench.btim
..........\.......\........\PLL_top_tbench.v
..........\.......\........\waveperl.log
..........\.......\.ynthesis\.recordref
..........\.......\.........\dm\PLL_top_1.xdm
..........\.......\.........\identify.log
..........\.......\.........\PLL_top.areasrr
..........\.......\.........\PLL_top.edn
..........\.......\.........\PLL_top.fse
..........\.......\.........\PLL_top.htm
..........\.......\.........\PLL_top.map
..........\.......\.........\PLL_top.sap
..........\.......\.........\PLL_top.sdf
..........\.......\.........\PLL_top.srd
..........\.......\.........\PLL_top.srm
..........\.......\.........\PLL_top.srr
..........\.......\.........\PLL_top.srs
..........\.......\.........\PLL_top.tlg
..........\.......\.........\PLL_top_1.areasr