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8位RISC CPU的VERILOG编程 SOURCECODE
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压缩包 : freerisc8_11.zip 列表 readme.txt Makefile VHDL/ Verilog/ www/ VHDL/ramlib_quartus.vhd VHDL/ramlib_sim.vhd VHDL/ramlib_xil.vhd Verilog/BASIC.HEX Verilog/DDS.HEX Verilog/alu.v Verilog/basic.asm Verilog/basic.rom Verilog/cpu.v Verilog/dds.asm Verilog/dds.rom Verilog/dram.v Verilog/exp.v Verilog/hex2v Verilog/hex2v.c Verilog/idec.v Verilog/pram.v Verilog/regs.v Verilog/runit Verilog/sindata.c Verilog/sindata.hex Verilog/test.v www/_borders/ www/_derived/ www/_fpclass/ www/_overlay/ www/_private/ www/_themes/ www/_vti_cnf/ www/_vti_pvt/ www/freerisc8_legal.htm www/images/ www/index.htm www/risc8_manual.htm www/risc8a.gif www/risc8a_small.gif www/_borders/_vti_cnf/ www/_borders/bottom.htm www/_borders/_vti_cnf/bottom.htm www/_derived/_vti_cnf/ www/_derived/freerisc8_legal.htm_cmp_expeditn110_vbtn.gif www/_derived/freerisc8_legal.htm_cmp_expeditn110_vbtn_a.gif www/_derived/index.htm_cmp_expeditn110_bnr.gif www/_derived/freerisc8_legal.htm_cmp_expeditn110_bnr.gif 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