文件名称:sc
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用verilog编写的乒乓球游戏，内带ps2，VGA驱动，下载到spantan3开发板上即可使用（原创）
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压缩包 : 99273873sc.rar 列表 sc\lrisc.ise sc\xilinxsim.ini sc\isim.log sc\isimwavedata.xwv sc\isim.hdlsourcefiles sc\__ISE_repository_lrisc.ise_.lock sc\test_RISC_SPM_isim_beh.exe sc\lrisc.ise_ISE_Backup sc\test_RISC_SPM_beh.prj sc\Alu_RISC_isim_beh.exe sc\test_RISC_SPM.v sc\Address_Register.v sc\Alu_RISC.v sc\Clock_Unit.v sc\Control_Unit.v sc\D_flop.v sc\Instruction_Register.v sc\Memory_Unit.v sc\Multiplexer_3ch.v sc\Multiplexer_5ch.v sc\Processing_Unit.v sc\Program_Counter.v sc\Register_Unit.v sc\RISC_SPM.v sc\Processing_Unit_summary.html sc\RISC_SPM_summary.html sc\isim.cmd sc\isim.tmp_save\_1 sc\isim.tmp_save sc\isim\work\hdllib.ref sc\isim\work\hdpdeps.ref sc\isim\work\_multiplexer__7ch\_multiplexer__7ch.h sc\isim\work\_multiplexer__7ch\mingw\_multiplexer__7ch.obj sc\isim\work\_multiplexer__7ch\mingw sc\isim\work\_multiplexer__7ch sc\isim\work\vlg08\_multiplexer__7ch.bin sc\isim\work\vlg08 sc\isim\work\_multiplexer__6ch\_multiplexer__6ch.h sc\isim\work\_multiplexer__6ch\mingw\_multiplexer__6ch.obj sc\isim\work\_multiplexer__6ch\mingw sc\isim\work\_multiplexer__6ch sc\isim\work\vlg6F\_multiplexer__6ch.bin sc\isim\work\vlg6F sc\isim\work\_r_i_s_c___s_p_m\_r_i_s_c___s_p_m.h sc\isim\work\_r_i_s_c___s_p_m\xsim_r_i_s_c___s_p_m.cpp sc\isim\work\_r_i_s_c___s_p_m\mingw\_r_i_s_c___s_p_m.obj sc\isim\work\_r_i_s_c___s_p_m\mingw sc\isim\work\_r_i_s_c___s_p_m sc\isim\work\vlg18\_r_i_s_c___s_p_m.bin sc\isim\work\vlg18 sc\isim\work\_control___unit\_control___unit.h sc\isim\work\_control___unit\xsim_control___unit.cpp sc\isim\work\_control___unit\mingw\_control___unit.obj sc\isim\work\_control___unit\mingw sc\isim\work\_control___unit sc\isim\work\_memory___unit\_memory___unit.h sc\isim\work\_memory___unit\mingw\_memory___unit.obj sc\isim\work\_memory___unit\mingw sc\isim\work\_memory___unit sc\isim\work\vlg4C\_memory___unit.bin sc\isim\work\vlg4C sc\isim\work\_processing___unit\_processing___unit.h sc\isim\work\_processing___unit\xsim_processing___unit.cpp sc\isim\work\_processing___unit\mingw\_processing___unit.obj sc\isim\work\_processing___unit\mingw sc\isim\work\_processing___unit sc\isim\work\vlg44\_processing___unit.bin sc\isim\work\vlg44 sc\isim\work\_address___register\_address___register.h sc\isim\work\_address___register\mingw\_address___register.obj sc\isim\work\_address___register\mingw sc\isim\work\_address___register sc\isim\work\vlg0A\_address___register.bin sc\isim\work\vlg0A sc\isim\work\_alu___r_i_s_c\_alu___r_i_s_c.h sc\isim\work\_alu___r_i_s_c\xsim_alu___r_i_s_c.cpp sc\isim\work\_alu___r_i_s_c\mingw\_alu___r_i_s_c.obj sc\isim\work\_alu___r_i_s_c\mingw sc\isim\work\_alu___r_i_s_c sc\isim\work\vlg6E\_alu___r_i_s_c.bin sc\isim\work\vlg6E sc\isim\work\_d__flop\_d__flop.h sc\isim\work\_d__flop\mingw\_d__flop.obj sc\isim\work\_d__flop\mingw sc\isim\work\_d__flop sc\isim\work\vlg78\_d__flop.bin sc\isim\work\vlg78 sc\isim\work\_instruction___register\_instruction___register.h sc\isim\work\_instruction___register\mingw\_instruction___register.obj sc\isim\work\_instruction___register\mingw sc\isim\work\_instruction___register sc\isim\work\vlg3A\_instruction___register.bin sc\isim\work\vlg3A sc\isim\work\_multiplexer__3ch\_multiplexer__3ch.h sc\isim\work\_multiplexer__3ch\mingw\_multiplexer__3ch.obj sc\isim\work\_multiplexer__3ch\mingw sc\isim\work\_multiplexer__3ch sc\isim\work\vlg24\_multiplexer__3ch.bin sc\isim\work\vlg24\_control___unit.bin sc\isim\work\vlg24 sc\isim\work\_multiplexer__5ch\_multiplexer__5ch.h sc\isim\work\_multiplexer__5ch\mingw\_multiplexer__5ch.obj sc\isim\work\_multiplexer__5ch\mingw sc\isim\work\_multiplexer__5ch sc\isim\work\vlg56\_multiplexer__5ch.bin sc\isim\work\vlg56 sc\isim\work\_program___counter\_program___counter.h sc\isim\work\_program___counter\mingw\_program___counter.obj sc\isim\work\_program___counter\mingw sc\isim\work\_program___counter sc\isim\work\vlg4B\_program___counter.bin sc\isim\work\vlg4B sc\isim\work\_register___unit\_register___unit.h sc\isim\work\_register___unit\mingw\_register___unit.obj sc\isim\work\_register___unit\mingw sc\isim\work\_register___unit sc\isim\work\vlg0C\_register___unit.bin sc\isim\work\vlg0C sc\isim\work\glbl\glbl.h sc\isim\work\glbl\mingw\glbl.obj sc\isim\work\glbl\mingw sc\isim\work\glbl sc\isim\work\vlg2D\glbl.bin sc\isim\work\vlg2D sc\isim\work\test___r_i_s_c___s_p_m\test___r_i_s_c___s_p_m.h sc\isim\work\test___r_i_s_c___s_p_m\xsimtest___r_i_s_c___s_p_m.cpp sc\isim\work\test___r_i_s_c___s_p_m\mingw\test___r_i_s_c___s_p_m.obj sc\isim\work\test___r_i_s_c___s_p_m\mingw sc\isim\work\test___r_i_s_c___s_p_m sc\isim\work\vlg1B\test___r_i_s_c___s_p_m.bin sc\isim\work\vlg1B sc\isim\work\_clock___unit\_clock___unit.h sc\isim\work\_clock___unit\mingw\_clock___unit.obj sc\isim\work\_clock___unit\mingw sc\isim\work\_clock___unit sc\isim\work\vlg2F\_clock___unit.bin sc\isim\work\vlg2F sc\isim\work sc\isim sc\_xmsgs\fuse.xmsgs sc\_xmsgs sc