文件名称:10vhdlexamples
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10个VHDL程序实例，包括加法器，全加器、函数发生器，选择器等。
(系统自动生成,下载前可以参看下载内容)
下载文件列表
压缩包 : 8140457510vhdlexamples.rar 列表 7_shiftreg\7_MVL7_functions.vhd 7_shiftreg\7_shiftreg.vhd 7_shiftreg\7_synthesis_types.vhd 7_shiftreg\7_test_vector.vhd 7_shiftreg\7_TYPES.VHD 7_shiftreg\README.TXT 8_BITPKG\8_BITPKG.VHD 8_BITPKG\8_bit_rtl_lib.vhd 8_BITPKG\README.TXT 9_MVL7_TYPES\9_MVL7_types.vhd 9_MVL7_TYPES\README.TXT 10_function\10_bit_to_int.vhd 10_function\README.TXT 1_ADDER\1_ADDER\1_ADDER.exp 1_ADDER\1_ADDER\files\L1.rpt 1_ADDER\1_ADDER\files\L2.rpt 1_ADDER\1_ADDER\files\L3.rpt 1_ADDER\1_ADDER\workdirs\aa\ADDER.sim 1_ADDER\1_ADDER\workdirs\aa\ADDER.syn 1_ADDER\1_ADDER\workdirs\aa\Anal.info 1_ADDER\1_ADDER\workdirs\aa\Anal.out 1_ADDER\1_ADDER\workdirs\WORK\Anal.info 1_ADDER\1_ADDER\workdirs\WORK\Anal.out 1_ADDER\1_ADDER\workdirs\WORK\BIT_RTL_ADDER.sim 1_ADDER\1_ADDER\workdirs\WORK\BIT_RTL_ADDER.syn 1_ADDER\1_adder.acf 1_ADDER\1_adder.hif 1_ADDER\1_adder.mmf 1_ADDER\1_ADDER.VHD 1_ADDER\bir_rtl_adder.acf 1_ADDER\bir_rtl_adder.hif 1_ADDER\bir_rtl_adder.mmf 1_ADDER\bir_rtl_adder.tdf 1_ADDER\bit_rtl_adder.acf 1_ADDER\bit_rtl_adder.hif 1_ADDER\bit_rtl_adder.mmf 1_ADDER\bit_rtl_adder.vhd 1_ADDER\LIB.DLS 1_ADDER\README.TXT 1_ADDER\transcript 1_ADDER\U2268397.DLS 1_ADDER\work\_info 2_ADDER\2_ADDER.VHD 2_ADDER\README.TXT 3_MUL\3_MUL.VHD 3_MUL\README.TXT 4_COMP\4_COMP.VHD 4_COMP\README.TXT 5_MUX2\5_MUX2.VHD 5_MUX2\README.TXT 6_REG\6_REG.VHD 6_REG\README.TXT 1_ADDER\1_ADDER\workdirs\aa 1_ADDER\1_ADDER\workdirs\WORK 1_ADDER\1_ADDER\files 1_ADDER\1_ADDER\workdirs 1_ADDER\1_ADDER 1_ADDER\work 7_shiftreg 8_BITPKG 9_MVL7_TYPES 10_function 1_ADDER 2_ADDER 3_MUL 4_COMP 5_MUX2 6_REG