文件名称:SDRAM

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [C/C++] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 12.26mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 陈*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

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在ISE环境下对SDRAM(异步动态存储器)的控制模块设计。-In the ISE environment of SDRAM ( asynchronous DRAM ) control module design.
(系统自动生成,下载前可以参看下载内容)

下载文件列表

SDRAM

.....\123.cpj

.....\Command.vhd

.....\control_interface.vhd

.....\device_usage_statistics.html

.....\fpga_sdram.bgn

.....\fpga_sdram.bit

.....\FPGA_SDRAM.bld

.....\FPGA_SDRAM.cel

.....\FPGA_SDRAM.cmd_log

.....\fpga_sdram.drc

.....\FPGA_SDRAM.lfp

.....\FPGA_SDRAM.lso

.....\fpga_sdram.msd

.....\fpga_sdram.msk

.....\FPGA_SDRAM.ncd

.....\FPGA_SDRAM.ngc

.....\FPGA_SDRAM.ngd

.....\FPGA_SDRAM.ngr

.....\FPGA_SDRAM.pad

.....\FPGA_SDRAM.par

.....\FPGA_SDRAM.pcf

.....\FPGA_SDRAM.prj

.....\fpga_sdram.rbb

.....\fpga_sdram.rbd

.....\FPGA_SDRAM.stx

.....\FPGA_SDRAM.syr

.....\fpga_sdram.twr

.....\fpga_sdram.twx

.....\FPGA_SDRAM.ucf

.....\FPGA_SDRAM.unroutes

.....\FPGA_SDRAM.ut

.....\FPGA_SDRAM.vhd

.....\FPGA_SDRAM.xpi

.....\FPGA_SDRAM.xst

.....\FPGA_SDRAM_cs.blc

.....\FPGA_SDRAM_cs.ngc

.....\FPGA_SDRAM_guide.ncd

.....\FPGA_SDRAM_last_par.ncd

.....\FPGA_SDRAM_map.map

.....\FPGA_SDRAM_map.mrp

.....\FPGA_SDRAM_map.ncd

.....\FPGA_SDRAM_map.ngm

.....\FPGA_SDRAM_pad.csv

.....\FPGA_SDRAM_pad.txt

.....\FPGA_SDRAM_prev_built.ngd

.....\FPGA_SDRAM_summary.html

.....\FPGA_SDRAM_summary.xml

.....\FPGA_SDRAM_usage.xml

.....\FPGA_SDRAM_vhdl.prj

.....\init.vhd

.....\isim

.....\isim.cmd

.....\isim.hdlsourcefiles

.....\isim.log

.....\isim.tmp_save

.....\.............\_1

.....\isimwavedata.xwv

.....\....\unisim.auxlib

.....\....\.............\bufg

.....\....\.............\....\bufg_v.h

.....\....\.............\....\mingw

.....\....\.............\....\.....\bufg_v.obj

.....\....\.............\dcm_adv

.....\....\.............\.......\dcm_adv_v.h

.....\....\.............\.......\mingw

.....\....\.............\.......\.....\dcm_adv_v.obj

.....\....\.............\dcm_adv_clock_divide_by_2

.....\....\.............\.........................\dcm_adv_clock_divide_by_2_v.h

.....\....\.............\.........................\mingw

.....\....\.............\.........................\.....\dcm_adv_clock_divide_by_2_v.obj

.....\....\.............\dcm_adv_clock_lost

.....\....\.............\..................\dcm_adv_clock_lost_v.h

.....\....\.............\..................\mingw

.....\....\.............\..................\.....\dcm_adv_clock_lost_v.obj

.....\....\.............\dcm_adv_maximum_period_check

.....\....\.............\............................\dcm_adv_maximum_period_check_v.h

.....\....\.............\............................\mingw

.....\....\.............\............................\.....\dcm_adv_maximum_period_check_v.obj

.....\....\.............\hdllib.ref

.....\....\.............\ibufg

.....\....\.............\.....\ibufg_v.h

.....\....\.............\.....\mingw

.....\....\.............\.....\.....\ibufg_v.obj

.....\....\.............\vcomponents

.....\....\.............\...........\mingw

.....\....\.............\...........\.....\vcomponents.obj

.....\....\.............\...........\vcomponents.h

.....\....\.............\vpkg

.....\....\.............\....\mingw

.....\....\.............\....\.....\vpkg.obj

.....\....\.............\....\vpkg.h

.....\....\work

.....\....\....\command

.....\....\....\.......\mingw

.....\....\....\.......\.....\rtl.obj

.....\....\....\.......\rtl.h

.....\....\....\control_interface

.....\....\....\.................\mingw

.....\....\....\.................\.....\rtl.obj

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