文件名称:EDA
介绍说明－－下载内容均来自于网络，请自行研究使用
毕业设计时设计的一个基于FIFO的乒乓机制，作用是不用等待当前数据接收完后再处理，提高数据吞吐量。-A graduate of the design in the design of a FIFO based on the ping pong mechanism, effect is not waiting for the current data received after processing, improve the data throughput
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下载文件列表
EDA\adder.bsf
...\adder.qip
...\adder.v
...\adder_bb.v
...\adder_syn.v
...\adder_wave0.jpg
...\adder_waveforms.html
...\control_state_machine.bsf
...\control_state_machine.v
...\control_state_machine.v.bak
...\db\add_sub_aub.tdf
...\..\add_sub_fgh.tdf
...\..\add_sub_gub.tdf
...\..\altsyncram_9pf1.tdf
...\..\altsyncram_tof1.tdf
...\..\alt_synch_pipe_jc8.tdf
...\..\alt_synch_pipe_kc8.tdf
...\..\alt_synch_pipe_pc8.tdf
...\..\alt_synch_pipe_qc8.tdf
...\..\a_fefifo_2bc.tdf
...\..\a_fefifo_6qc.tdf
...\..\a_fefifo_bqc.tdf
...\..\a_fefifo_ctc.tdf
...\..\a_gray2bin_k4b.tdf
...\..\a_gray2bin_q4b.tdf
...\..\a_graycounter_o06.tdf
...\..\a_graycounter_u06.tdf
...\..\cntr_6ta.tdf
...\..\cntr_cta.tdf
...\..\dcfifo_0pj1.tdf
...\..\dcfifo_b9n1.tdf
...\..\dcfifo_e9n1.tdf
...\..\dcfifo_rdi1.tdf
...\..\dffpipe_ad9.tdf
...\..\dffpipe_dd9.tdf
...\..\dffpipe_ed9.tdf
...\..\dffpipe_gd9.tdf
...\..\dffpipe_jd9.tdf
...\..\dffpipe_kd9.tdf
...\..\dpram_ou11.tdf
...\..\dpram_uu11.tdf
...\..\FPGA.analyze_file.qmsg
...\..\FPGA.asm.qmsg
...\..\FPGA.cbx.xml
...\..\FPGA.cmp.bpm
...\..\FPGA.cmp.cdb
...\..\FPGA.cmp.ecobp
...\..\FPGA.cmp.hdb
...\..\FPGA.cmp.kpt
...\..\FPGA.cmp.logdb
...\..\FPGA.cmp.rdb
...\..\FPGA.cmp.tdb
...\..\FPGA.cmp0.ddb
...\..\FPGA.cmp_merge.kpt
...\..\FPGA.db_info
...\..\FPGA.eco.cdb
...\..\FPGA.fit.qmsg
...\..\FPGA.hier_info
...\..\FPGA.hif
...\..\FPGA.lpc.html
...\..\FPGA.lpc.rdb
...\..\FPGA.lpc.txt
...\..\FPGA.map.bpm
...\..\FPGA.map.cdb
...\..\FPGA.map.ecobp
...\..\FPGA.map.hdb
...\..\FPGA.map.kpt
...\..\FPGA.map.logdb
...\..\FPGA.map.qmsg
...\..\FPGA.map_bb.cdb
...\..\FPGA.map_bb.hdb
...\..\FPGA.map_bb.logdb
...\..\FPGA.pre_map.cdb
...\..\FPGA.pre_map.hdb
...\..\FPGA.rtlv.hdb
...\..\FPGA.rtlv_sg.cdb
...\..\FPGA.rtlv_sg_swap.cdb
...\..\FPGA.sgdiff.cdb
...\..\FPGA.sgdiff.hdb
...\..\FPGA.sld_design_entry.sci
...\..\FPGA.sld_design_entry_dsc.sci
...\..\FPGA.smp_dump.txt
...\..\FPGA.syn_hier_info
...\..\FPGA.tan.qmsg
...\..\FPGA.tis_db_list.ddb
...\..\FPGA.tmw_info
...\..\FPGA_global_asgn_op.abo
...\..\prev_cmp_FPGA.map.qmsg
...\..\prev_cmp_FPGA.qmsg
...\FPGA.asm.rpt
...\FPGA.bdf
...\FPGA.done
...\FPGA.fit.rpt
...\FPGA.fit.smsg
...\FPGA.fit.summary
...\FPGA.flow.rpt
...\FPGA.map.rpt
...\FPGA.map.summary
...\FPGA.pin
...\FPGA.pof
...\adder.qip
...\adder.v
...\adder_bb.v
...\adder_syn.v
...\adder_wave0.jpg
...\adder_waveforms.html
...\control_state_machine.bsf
...\control_state_machine.v
...\control_state_machine.v.bak
...\db\add_sub_aub.tdf
...\..\add_sub_fgh.tdf
...\..\add_sub_gub.tdf
...\..\altsyncram_9pf1.tdf
...\..\altsyncram_tof1.tdf
...\..\alt_synch_pipe_jc8.tdf
...\..\alt_synch_pipe_kc8.tdf
...\..\alt_synch_pipe_pc8.tdf
...\..\alt_synch_pipe_qc8.tdf
...\..\a_fefifo_2bc.tdf
...\..\a_fefifo_6qc.tdf
...\..\a_fefifo_bqc.tdf
...\..\a_fefifo_ctc.tdf
...\..\a_gray2bin_k4b.tdf
...\..\a_gray2bin_q4b.tdf
...\..\a_graycounter_o06.tdf
...\..\a_graycounter_u06.tdf
...\..\cntr_6ta.tdf
...\..\cntr_cta.tdf
...\..\dcfifo_0pj1.tdf
...\..\dcfifo_b9n1.tdf
...\..\dcfifo_e9n1.tdf
...\..\dcfifo_rdi1.tdf
...\..\dffpipe_ad9.tdf
...\..\dffpipe_dd9.tdf
...\..\dffpipe_ed9.tdf
...\..\dffpipe_gd9.tdf
...\..\dffpipe_jd9.tdf
...\..\dffpipe_kd9.tdf
...\..\dpram_ou11.tdf
...\..\dpram_uu11.tdf
...\..\FPGA.analyze_file.qmsg
...\..\FPGA.asm.qmsg
...\..\FPGA.cbx.xml
...\..\FPGA.cmp.bpm
...\..\FPGA.cmp.cdb
...\..\FPGA.cmp.ecobp
...\..\FPGA.cmp.hdb
...\..\FPGA.cmp.kpt
...\..\FPGA.cmp.logdb
...\..\FPGA.cmp.rdb
...\..\FPGA.cmp.tdb
...\..\FPGA.cmp0.ddb
...\..\FPGA.cmp_merge.kpt
...\..\FPGA.db_info
...\..\FPGA.eco.cdb
...\..\FPGA.fit.qmsg
...\..\FPGA.hier_info
...\..\FPGA.hif
...\..\FPGA.lpc.html
...\..\FPGA.lpc.rdb
...\..\FPGA.lpc.txt
...\..\FPGA.map.bpm
...\..\FPGA.map.cdb
...\..\FPGA.map.ecobp
...\..\FPGA.map.hdb
...\..\FPGA.map.kpt
...\..\FPGA.map.logdb
...\..\FPGA.map.qmsg
...\..\FPGA.map_bb.cdb
...\..\FPGA.map_bb.hdb
...\..\FPGA.map_bb.logdb
...\..\FPGA.pre_map.cdb
...\..\FPGA.pre_map.hdb
...\..\FPGA.rtlv.hdb
...\..\FPGA.rtlv_sg.cdb
...\..\FPGA.rtlv_sg_swap.cdb
...\..\FPGA.sgdiff.cdb
...\..\FPGA.sgdiff.hdb
...\..\FPGA.sld_design_entry.sci
...\..\FPGA.sld_design_entry_dsc.sci
...\..\FPGA.smp_dump.txt
...\..\FPGA.syn_hier_info
...\..\FPGA.tan.qmsg
...\..\FPGA.tis_db_list.ddb
...\..\FPGA.tmw_info
...\..\FPGA_global_asgn_op.abo
...\..\prev_cmp_FPGA.map.qmsg
...\..\prev_cmp_FPGA.qmsg
...\FPGA.asm.rpt
...\FPGA.bdf
...\FPGA.done
...\FPGA.fit.rpt
...\FPGA.fit.smsg
...\FPGA.fit.summary
...\FPGA.flow.rpt
...\FPGA.map.rpt
...\FPGA.map.summary
...\FPGA.pin
...\FPGA.pof