文件名称:uart_verilog
- 所属分类：
- VHDL编程
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 5kb
- 下载次数：
- 0次
- 提 供 者：
- vijend******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection.
This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This is a 3V, 128 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
-The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection.
This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This is a 3V, 128 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This is a 3V, 128 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
-The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and overrun detection.
This design is targeted to the XCR3128XL-7VQ100C CoolRunner CPLD. This is a 3V, 128 macrocell device in a 100 VQFP package. The fitter was allowed to pick the pin-out for the device.
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下载文件列表
uart_verilog\rcvr.v
............\rcvr_tf.v
............\readme.txt
............\txmit.v
............\txmit_tf.v
............\uart.v
uart_verilog
............\rcvr_tf.v
............\readme.txt
............\txmit.v
............\txmit_tf.v
............\uart.v
uart_verilog