文件名称:verilog-UART-Controler
介绍说明－－下载内容均来自于网络，请自行研究使用
使用verilog语言实现的UART控制器，包含发送和接收部分，波特率可调。-Using the UART controller verilog language, including sending and receiving part, the baud rate is adjustable.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
verilog UART Controler\db\mytest.db_info
......................\..\mytest.eco.cdb
......................\..\mytest.sim.cvwf
......................\..\mytest.sld_design_entry.sci
......................\..\prev_cmp_mytest.asm.qmsg
......................\..\prev_cmp_mytest.fit.qmsg
......................\..\prev_cmp_mytest.map.qmsg
......................\..\prev_cmp_mytest.qmsg
......................\..\prev_cmp_mytest.sim.qmsg
......................\..\prev_cmp_mytest.sta.qmsg
......................\..\wed.wsf
......................\incremental_db\compiled_partitions\mytest.root_partition.cmp.atm
......................\..............\...................\mytest.root_partition.cmp.dfp
......................\..............\...................\mytest.root_partition.cmp.hdbx
......................\..............\...................\mytest.root_partition.cmp.kpt
......................\..............\...................\mytest.root_partition.cmp.logdb
......................\..............\...................\mytest.root_partition.cmp.rcf
......................\..............\...................\mytest.root_partition.map.atm
......................\..............\...................\mytest.root_partition.map.dpi
......................\..............\...................\mytest.root_partition.map.hdbx
......................\..............\...................\mytest.root_partition.map.kpt
......................\..............\README
......................\mytest.asm.rpt
......................\mytest.done
......................\mytest.fit.rpt
......................\mytest.fit.smsg
......................\mytest.fit.summary
......................\mytest.flow.rpt
......................\mytest.map.rpt
......................\mytest.map.smsg
......................\mytest.map.summary
......................\mytest.pin
......................\mytest.qpf
......................\mytest.qsf
......................\mytest.qws
......................\mytest.sim.rpt
......................\mytest.sof
......................\mytest.sta.rpt
......................\mytest.sta.summary
......................\mytest.v
......................\mytest.v.bak
......................\mytest.vwf
......................\UART.vhd
......................\URAT.v
......................\incremental_db\compiled_partitions
......................\db
......................\incremental_db
verilog UART Controler
......................\..\mytest.eco.cdb
......................\..\mytest.sim.cvwf
......................\..\mytest.sld_design_entry.sci
......................\..\prev_cmp_mytest.asm.qmsg
......................\..\prev_cmp_mytest.fit.qmsg
......................\..\prev_cmp_mytest.map.qmsg
......................\..\prev_cmp_mytest.qmsg
......................\..\prev_cmp_mytest.sim.qmsg
......................\..\prev_cmp_mytest.sta.qmsg
......................\..\wed.wsf
......................\incremental_db\compiled_partitions\mytest.root_partition.cmp.atm
......................\..............\...................\mytest.root_partition.cmp.dfp
......................\..............\...................\mytest.root_partition.cmp.hdbx
......................\..............\...................\mytest.root_partition.cmp.kpt
......................\..............\...................\mytest.root_partition.cmp.logdb
......................\..............\...................\mytest.root_partition.cmp.rcf
......................\..............\...................\mytest.root_partition.map.atm
......................\..............\...................\mytest.root_partition.map.dpi
......................\..............\...................\mytest.root_partition.map.hdbx
......................\..............\...................\mytest.root_partition.map.kpt
......................\..............\README
......................\mytest.asm.rpt
......................\mytest.done
......................\mytest.fit.rpt
......................\mytest.fit.smsg
......................\mytest.fit.summary
......................\mytest.flow.rpt
......................\mytest.map.rpt
......................\mytest.map.smsg
......................\mytest.map.summary
......................\mytest.pin
......................\mytest.qpf
......................\mytest.qsf
......................\mytest.qws
......................\mytest.sim.rpt
......................\mytest.sof
......................\mytest.sta.rpt
......................\mytest.sta.summary
......................\mytest.v
......................\mytest.v.bak
......................\mytest.vwf
......................\UART.vhd
......................\URAT.v
......................\incremental_db\compiled_partitions
......................\db
......................\incremental_db
verilog UART Controler