文件名称:digitron_driver_VHD
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关于easy fpga开发板的led数码管的驱动；
--输入：控制端ctrl_digin[2:0]共三位，表示（0~7）控制8个数码管的选通，
-- 数据端dig_dtin[3:0]共四位，表示（0~F）控制数码管显示的数字
-- 控制时钟clk_dig一位用于时钟同步
--输出：显示dig_dtout[6:0]共七位，控制A,B,C,D,E,F,G[6:0]小数点不包括在内；
-- 控制位ctrl_digout[7:0]共八位，任意时刻只能有一个为高，即只有一个数码管显示，为共阳极的；
--要求：输入信号：ctrl_digin，dig_dtout,clk_dig一定要稳定-On easy fpga development board led digital tube-driven
- Input: Control side ctrl_digin [2:0] a total of three, that (0 to 7) control 8 digital strobe,
- Data terminal dig_dtin [3:0] a total of four, said (0 ~ F) control the number of digital display
- Control the clock for clock synchronization clk_dig a
- Output: Displays dig_dtout [6:0] a total of seven, control A, B, C, D, E, F, G [6:0] decimal point is not included
- Control bits ctrl_digout [7:0] of eight, at any time only one high that only a digital display, for a total of anode
- Requirements: Input signal: ctrl_digin, dig_dtout, clk_dig must be stable
--输入：控制端ctrl_digin[2:0]共三位，表示（0~7）控制8个数码管的选通，
-- 数据端dig_dtin[3:0]共四位，表示（0~F）控制数码管显示的数字
-- 控制时钟clk_dig一位用于时钟同步
--输出：显示dig_dtout[6:0]共七位，控制A,B,C,D,E,F,G[6:0]小数点不包括在内；
-- 控制位ctrl_digout[7:0]共八位，任意时刻只能有一个为高，即只有一个数码管显示，为共阳极的；
--要求：输入信号：ctrl_digin，dig_dtout,clk_dig一定要稳定-On easy fpga development board led digital tube-driven
- Input: Control side ctrl_digin [2:0] a total of three, that (0 to 7) control 8 digital strobe,
- Data terminal dig_dtin [3:0] a total of four, said (0 ~ F) control the number of digital display
- Control the clock for clock synchronization clk_dig a
- Output: Displays dig_dtout [6:0] a total of seven, control A, B, C, D, E, F, G [6:0] decimal point is not included
- Control bits ctrl_digout [7:0] of eight, at any time only one high that only a digital display, for a total of anode
- Requirements: Input signal: ctrl_digin, dig_dtout, clk_dig must be stable
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digitron_driver.vhd