文件名称:Chapter-7
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- VHDL编程
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- [VHDL] [源码]
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- 2012-11-26
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- 7kb
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- shixi******
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练习七在verilog hdl中使用任务（task）319
-• Source code of designs in chapters 1 to 8.
• Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files.
• Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip”
• The OVL directory has OVL library version 1.0 and its documentations
• In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition.
• In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
-• Source code of designs in chapters 1 to 8.
• Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files.
• Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip”
• The OVL directory has OVL library version 1.0 and its documentations
• In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition.
• In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
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下载文件列表
Chapter 7\an_nmos.v
.........\aoi_3d.v
.........\barrel_shifter.v
.........\barrel_shifter_reg.v
.........\cross_couple.v
.........\dynamic_cell.v
.........\d_latch.v
.........\half_reg.v
.........\master_slave_dff.v
.........\mos_strength.v
.........\nand2_1d.v
.........\Problem6.v
.........\register_4.v
.........\shifter.v
.........\test_an_nmos.v
.........\test_aoi_3d.v
.........\test_barrel_shifter.v
.........\test_barrel_shifter_reg.v
.........\test_cross_couple.v
.........\test_dynamic_cell.v
.........\test_d_latch.v
.........\test_half_reg.v
.........\test_master_slave_dff.v
.........\test_mos_strength.v
.........\test_nand2_1d.v
.........\test_register_4.v
.........\test_shifter.v
.........\test_wired_strength.v
.........\wired_strength.v
Chapter 7
.........\aoi_3d.v
.........\barrel_shifter.v
.........\barrel_shifter_reg.v
.........\cross_couple.v
.........\dynamic_cell.v
.........\d_latch.v
.........\half_reg.v
.........\master_slave_dff.v
.........\mos_strength.v
.........\nand2_1d.v
.........\Problem6.v
.........\register_4.v
.........\shifter.v
.........\test_an_nmos.v
.........\test_aoi_3d.v
.........\test_barrel_shifter.v
.........\test_barrel_shifter_reg.v
.........\test_cross_couple.v
.........\test_dynamic_cell.v
.........\test_d_latch.v
.........\test_half_reg.v
.........\test_master_slave_dff.v
.........\test_mos_strength.v
.........\test_nand2_1d.v
.........\test_register_4.v
.........\test_shifter.v
.........\test_wired_strength.v
.........\wired_strength.v
Chapter 7