文件名称:sdram_vhdl
介绍说明－－下载内容均来自于网络，请自行研究使用
DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的。-DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
sdram_vhdl
..........\sdram_doc
..........\.........\ddr_sdram.pdf
..........\sdram_r
..........\.......\mt46v4m16.v
..........\sdram_readme.txt
..........\sdram_route
..........\...........\ddr_sdram.csf
..........\...........\ddr_sdram.esf
..........\...........\ddr_sdram.psf
..........\...........\ddr_sdram.quartus
..........\...........\ddr_sdram.vqm
..........\...........\pll1.v
..........\sdram_simulation
..........\................\ddr_compile_all.v
..........\................\ddr_sdram_tb.v
..........\................\modelsim.ini
..........\................\readme.txt
..........\................\work
..........\................\....\altclklock
..........\................\....\..........\verilog.psm
..........\................\....\..........\_primary.dat
..........\................\....\..........\_primary.vhd
..........\................\....\ddr_command
..........\................\....\...........\verilog.psm
..........\................\....\...........\_primary.dat
..........\................\....\...........\_primary.vhd
..........\................\....\ddr_control_interface
..........\................\....\.....................\verilog.psm
..........\................\....\.....................\_primary.dat
..........\................\....\.....................\_primary.vhd
..........\................\....\ddr_data_path
..........\................\....\.............\verilog.psm
..........\................\....\.............\_primary.dat
..........\................\....\.............\_primary.vhd
..........\................\....\ddr_sdram
..........\................\....\.........\verilog.psm
..........\................\....\.........\_primary.dat
..........\................\....\.........\_primary.vhd
..........\................\....\ddr_sdram_tb
..........\................\....\............\verilog.psm
..........\................\....\............\_primary.dat
..........\................\....\............\_primary.vhd
..........\................\....\mt46v4m16
..........\................\....\.........\verilog.psm
..........\................\....\.........\_primary.dat
..........\................\....\.........\_primary.vhd
..........\................\....\pll1
..........\................\....\....\verilog.psm
..........\................\....\....\_primary.dat
..........\................\....\....\_primary.vhd
..........\................\....\_info
..........\sdram_source
..........\............\altclklock.v
..........\............\ddr_Command.v
..........\............\ddr_control_interface.v
..........\............\ddr_data_path.v
..........\............\ddr_sdram.v
..........\............\Params.v
..........\............\pll1.v
..........\sdram_synthesis
..........\...............\synplicity
..........\...............\..........\ddr_data_path.srm
..........\...............\..........\ddr_data_path.srr
..........\...............\..........\ddr_data_path.srs
..........\...............\..........\ddr_data_path.tlg
..........\...............\..........\ddr_data_path.xrf
..........\...............\..........\ddr_sdram.prj
..........\...............\..........\ddr_sdram.sdc
..........\...............\..........\ddr_sdram.srm
..........\...............\..........\ddr_sdram.srr
..........\...............\..........\ddr_sdram.srs
..........\...............\..........\ddr_sdram.tcl
..........\...............\..........\ddr_sdram.tlg
..........\...............\..........\ddr_sdram.vqm
..........\...............\..........\ddr_sdram.xrf
..........\...............\..........\ddr_sdram_cons.tcl
..........\...............\..........\ddr_sdram_rm.tcl
..........\sdram_doc
..........\.........\ddr_sdram.pdf
..........\sdram_r
..........\.......\mt46v4m16.v
..........\sdram_readme.txt
..........\sdram_route
..........\...........\ddr_sdram.csf
..........\...........\ddr_sdram.esf
..........\...........\ddr_sdram.psf
..........\...........\ddr_sdram.quartus
..........\...........\ddr_sdram.vqm
..........\...........\pll1.v
..........\sdram_simulation
..........\................\ddr_compile_all.v
..........\................\ddr_sdram_tb.v
..........\................\modelsim.ini
..........\................\readme.txt
..........\................\work
..........\................\....\altclklock
..........\................\....\..........\verilog.psm
..........\................\....\..........\_primary.dat
..........\................\....\..........\_primary.vhd
..........\................\....\ddr_command
..........\................\....\...........\verilog.psm
..........\................\....\...........\_primary.dat
..........\................\....\...........\_primary.vhd
..........\................\....\ddr_control_interface
..........\................\....\.....................\verilog.psm
..........\................\....\.....................\_primary.dat
..........\................\....\.....................\_primary.vhd
..........\................\....\ddr_data_path
..........\................\....\.............\verilog.psm
..........\................\....\.............\_primary.dat
..........\................\....\.............\_primary.vhd
..........\................\....\ddr_sdram
..........\................\....\.........\verilog.psm
..........\................\....\.........\_primary.dat
..........\................\....\.........\_primary.vhd
..........\................\....\ddr_sdram_tb
..........\................\....\............\verilog.psm
..........\................\....\............\_primary.dat
..........\................\....\............\_primary.vhd
..........\................\....\mt46v4m16
..........\................\....\.........\verilog.psm
..........\................\....\.........\_primary.dat
..........\................\....\.........\_primary.vhd
..........\................\....\pll1
..........\................\....\....\verilog.psm
..........\................\....\....\_primary.dat
..........\................\....\....\_primary.vhd
..........\................\....\_info
..........\sdram_source
..........\............\altclklock.v
..........\............\ddr_Command.v
..........\............\ddr_control_interface.v
..........\............\ddr_data_path.v
..........\............\ddr_sdram.v
..........\............\Params.v
..........\............\pll1.v
..........\sdram_synthesis
..........\...............\synplicity
..........\...............\..........\ddr_data_path.srm
..........\...............\..........\ddr_data_path.srr
..........\...............\..........\ddr_data_path.srs
..........\...............\..........\ddr_data_path.tlg
..........\...............\..........\ddr_data_path.xrf
..........\...............\..........\ddr_sdram.prj
..........\...............\..........\ddr_sdram.sdc
..........\...............\..........\ddr_sdram.srm
..........\...............\..........\ddr_sdram.srr
..........\...............\..........\ddr_sdram.srs
..........\...............\..........\ddr_sdram.tcl
..........\...............\..........\ddr_sdram.tlg
..........\...............\..........\ddr_sdram.vqm
..........\...............\..........\ddr_sdram.xrf
..........\...............\..........\ddr_sdram_cons.tcl
..........\...............\..........\ddr_sdram_rm.tcl