文件名称:IDE_Interface
介绍说明－－下载内容均来自于网络，请自行研究使用
IDE接口程序，是用VERILOG写的，高手进阶程序-IDE interface program is written using VERILOG, master advanced procedures. .
相关搜索： IDE
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ATA\ata\trunk\bench\verilog\ata_device.v
...\...\.....\.....\.......\tests.v
...\...\.....\.....\.......\test_bench_top.v
...\...\.....\.....\.......\wb_mast_model.v
...\...\.....\.....\.......\wb_model_defines.v
...\...\.....\.....\.......\wb_slv_model.v
...\...\.....\doc\preliminary_ata_core.pdf
...\...\.....\...\src\ata_core.doc
...\...\.....\rtl\verilog\ocidec-1\atahost_controller.v
...\...\.....\...\.......\........\atahost_pio_tctrl.v
...\...\.....\...\.......\........\atahost_top.v
...\...\.....\...\.......\........\atahost_wb_slave.v
...\...\.....\...\.......\........\revision_history.txt
...\...\.....\...\.......\........\ro_cnt.v
...\...\.....\...\.......\........\timescale.v
...\...\.....\...\.......\........\ud_cnt.v
...\...\.....\...\.......\.......2\atahost_controller.v
...\...\.....\...\.......\........\atahost_pio_actrl.v
...\...\.....\...\.......\........\atahost_pio_tctrl.v
...\...\.....\...\.......\........\atahost_top.v
...\...\.....\...\.......\........\atahost_wb_slave.v
...\...\.....\...\.......\........\revision_history.txt
...\...\.....\...\.......\........\ro_cnt.v
...\...\.....\...\.......\........\timescale.v
...\...\.....\...\.......\........\ud_cnt.v
...\...\.....\...\.hdl\ocidec1\atahost_controller.vhd
...\...\.....\...\....\.......\atahost_pio_tctrl.vhd
...\...\.....\...\....\.......\atahost_top.vhd
...\...\.....\...\....\.......\atahost_wb_slave.vhd
...\...\.....\...\....\.......\revision_history.txt
...\...\.....\...\....\.......\ro_cnt.vhd
...\...\.....\...\....\.......\ud_cnt.vhd
...\...\.....\...\....\......2\atahost_controller.vhd
...\...\.....\...\....\.......\atahost_pio_actrl.vhd
...\...\.....\...\....\.......\atahost_pio_tctrl.vhd
...\...\.....\...\....\.......\atahost_top.vhd
...\...\.....\...\....\.......\atahost_wb_slave.vhd
...\...\.....\...\....\.......\revision_history.txt
...\...\.....\...\....\.......\ro_cnt.vhd
...\...\.....\...\....\.......\ud_cnt.vhd
...\...\.....\...\....\......3\atahost_controller.vhd
...\...\.....\...\....\.......\atahost_dma_actrl.vhd
...\...\.....\...\....\.......\atahost_dma_tctrl.vhd
...\...\.....\...\....\.......\atahost_fifo.vhd
...\...\.....\...\....\.......\atahost_lfsr.vhd
...\...\.....\...\....\.......\atahost_pio_actrl.vhd
...\...\.....\...\....\.......\atahost_pio_controller.vhd
...\...\.....\...\....\.......\atahost_pio_tctrl.vhd
...\...\.....\...\....\.......\atahost_reg_buf.vhd
...\...\.....\...\....\.......\atahost_top.vhd
...\...\.....\...\....\.......\atahost_wb_slave.vhd
...\...\.....\...\....\.......\revision_history.txt
...\...\.....\...\....\.......\ro_cnt.vhd
...\...\.....\...\....\.......\ud_cnt.vhd
...\...\.....\sim\rtl_sim\bin\Makefile
...\...\.....\.yn\bin\comp.dc
...\...\.....\...\...\design_spec.dc
...\...\.....\...\...\lib_spec.dc
...\...\.....\...\...\read.dc
...\...\web_uploads\index.shtml
...\...\...........\preliminary_ata_core.pdf
...\使用说明请参看右侧注释====〉〉.txt
...\ata\trunk\rtl\verilog\ocidec-1
...\...\.....\...\.......\ocidec-2
...\...\.....\...\.hdl\ocidec1
...\...\.....\...\....\ocidec2
...\...\.....\...\....\ocidec3
...\...\.....\sim\rtl_sim\bin
...\...\.....\bench\verilog
...\...\.....\doc\src
...\...\.....\rtl\verilog
...\...\.....\...\vhdl
...\...\.....\sim\rtl_sim
...\...\.....\.yn\bin
...\...\.....\bench
...\...\.....\doc
...\...\.....\rtl
...\...\.....\sim
...\...\.....\syn
...\...\branches
...\...\tags
...\...\trunk
...\...\web_uploads
...\ata
ATA
...\...\.....\.....\.......\tests.v
...\...\.....\.....\.......\test_bench_top.v
...\...\.....\.....\.......\wb_mast_model.v
...\...\.....\.....\.......\wb_model_defines.v
...\...\.....\.....\.......\wb_slv_model.v
...\...\.....\doc\preliminary_ata_core.pdf
...\...\.....\...\src\ata_core.doc
...\...\.....\rtl\verilog\ocidec-1\atahost_controller.v
...\...\.....\...\.......\........\atahost_pio_tctrl.v
...\...\.....\...\.......\........\atahost_top.v
...\...\.....\...\.......\........\atahost_wb_slave.v
...\...\.....\...\.......\........\revision_history.txt
...\...\.....\...\.......\........\ro_cnt.v
...\...\.....\...\.......\........\timescale.v
...\...\.....\...\.......\........\ud_cnt.v
...\...\.....\...\.......\.......2\atahost_controller.v
...\...\.....\...\.......\........\atahost_pio_actrl.v
...\...\.....\...\.......\........\atahost_pio_tctrl.v
...\...\.....\...\.......\........\atahost_top.v
...\...\.....\...\.......\........\atahost_wb_slave.v
...\...\.....\...\.......\........\revision_history.txt
...\...\.....\...\.......\........\ro_cnt.v
...\...\.....\...\.......\........\timescale.v
...\...\.....\...\.......\........\ud_cnt.v
...\...\.....\...\.hdl\ocidec1\atahost_controller.vhd
...\...\.....\...\....\.......\atahost_pio_tctrl.vhd
...\...\.....\...\....\.......\atahost_top.vhd
...\...\.....\...\....\.......\atahost_wb_slave.vhd
...\...\.....\...\....\.......\revision_history.txt
...\...\.....\...\....\.......\ro_cnt.vhd
...\...\.....\...\....\.......\ud_cnt.vhd
...\...\.....\...\....\......2\atahost_controller.vhd
...\...\.....\...\....\.......\atahost_pio_actrl.vhd
...\...\.....\...\....\.......\atahost_pio_tctrl.vhd
...\...\.....\...\....\.......\atahost_top.vhd
...\...\.....\...\....\.......\atahost_wb_slave.vhd
...\...\.....\...\....\.......\revision_history.txt
...\...\.....\...\....\.......\ro_cnt.vhd
...\...\.....\...\....\.......\ud_cnt.vhd
...\...\.....\...\....\......3\atahost_controller.vhd
...\...\.....\...\....\.......\atahost_dma_actrl.vhd
...\...\.....\...\....\.......\atahost_dma_tctrl.vhd
...\...\.....\...\....\.......\atahost_fifo.vhd
...\...\.....\...\....\.......\atahost_lfsr.vhd
...\...\.....\...\....\.......\atahost_pio_actrl.vhd
...\...\.....\...\....\.......\atahost_pio_controller.vhd
...\...\.....\...\....\.......\atahost_pio_tctrl.vhd
...\...\.....\...\....\.......\atahost_reg_buf.vhd
...\...\.....\...\....\.......\atahost_top.vhd
...\...\.....\...\....\.......\atahost_wb_slave.vhd
...\...\.....\...\....\.......\revision_history.txt
...\...\.....\...\....\.......\ro_cnt.vhd
...\...\.....\...\....\.......\ud_cnt.vhd
...\...\.....\sim\rtl_sim\bin\Makefile
...\...\.....\.yn\bin\comp.dc
...\...\.....\...\...\design_spec.dc
...\...\.....\...\...\lib_spec.dc
...\...\.....\...\...\read.dc
...\...\web_uploads\index.shtml
...\...\...........\preliminary_ata_core.pdf
...\使用说明请参看右侧注释====〉〉.txt
...\ata\trunk\rtl\verilog\ocidec-1
...\...\.....\...\.......\ocidec-2
...\...\.....\...\.hdl\ocidec1
...\...\.....\...\....\ocidec2
...\...\.....\...\....\ocidec3
...\...\.....\sim\rtl_sim\bin
...\...\.....\bench\verilog
...\...\.....\doc\src
...\...\.....\rtl\verilog
...\...\.....\...\vhdl
...\...\.....\sim\rtl_sim
...\...\.....\.yn\bin
...\...\.....\bench
...\...\.....\doc
...\...\.....\rtl
...\...\.....\sim
...\...\.....\syn
...\...\branches
...\...\tags
...\...\trunk
...\...\web_uploads
...\ata
ATA