文件名称:Computer-Architecture-lab1
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计算机组成实验作业1，fpga开发板，verilog语言编写-Composition of experimental computer operating 1, fpga development board, verilog language
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09级计组实验_B班_31组_5090309744_谢聪_实验1代码\lab1.gise
...............................................\lab1.ise
...............................................\lab1.xise
...............................................\lab1_pa.log
...............................................\lab1_pa_ports.v
...............................................\.....xdb\tmp\ise\version
...............................................\........\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject
...............................................\........\...\...\............\..................\.........\HDProject_StrTbl
...............................................\........\...\...\............\..................\__stored_object_table__
...............................................\........\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
...............................................\........\...\...\............\.........\.......\RunOnce_tcl_StrTbl
...............................................\........\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
...............................................\........\...\...\............\................\................\dpm_project_main_StrTbl
...............................................\........\...\...\............\................Gui\CViewSelector
...............................................\........\...\...\............\...................\CViewSelector_StrTbl
...............................................\........\...\...\............\...................\File-SynthesisOnly
...............................................\........\...\...\............\...................\File-SynthesisOnly_StrTbl
...............................................\........\...\...\............\...................\Library-SynthesisOnly
...............................................\........\...\...\............\...................\Library-SynthesisOnly_StrTbl
...............................................\........\...\...\............\...................\Process-BehavioralSim-
...............................................\........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG
...............................................\........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG_StrTbl
...............................................\........\...\...\............\...................\Process-BehavioralSim-_StrTbl
...............................................\........\...\...\............\...................\Process-SynthesisOnly-
...............................................\........\...\...\............\...................\Process-SynthesisOnly-DESUT_UCF
...............................................\........\...\...\............\...................\Process-SynthesisOnly-DESUT_UCF_StrTbl
...............................................\........\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG
...............................................\........\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG_StrTbl
...............................................\........\...\...\............\...................\Process-SynthesisOnly-_StrTbl
...............................................\........\...\...\............\...................\Source-BehavioralSim-AutoCompile
...............................................\........\...\...\............\...................\Source-BehavioralSim-AutoCompile_StrTbl
...............................................\........\...\...\............\...................\Source-SynthesisOnly-AutoCompile
...............................................\........\...\...\............\...................\Source-SynthesisOnly-AutoCompile_StrTbl
...............................................\........\...\...\............\xreport\Gc_RvReportViewer-Current-Module
...............................................\........\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl
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...............................................\lab1.ise
...............................................\lab1.xise
...............................................\lab1_pa.log
...............................................\lab1_pa_ports.v
...............................................\.....xdb\tmp\ise\version
...............................................\........\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject
...............................................\........\...\...\............\..................\.........\HDProject_StrTbl
...............................................\........\...\...\............\..................\__stored_object_table__
...............................................\........\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
...............................................\........\...\...\............\.........\.......\RunOnce_tcl_StrTbl
...............................................\........\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
...............................................\........\...\...\............\................\................\dpm_project_main_StrTbl
...............................................\........\...\...\............\................Gui\CViewSelector
...............................................\........\...\...\............\...................\CViewSelector_StrTbl
...............................................\........\...\...\............\...................\File-SynthesisOnly
...............................................\........\...\...\............\...................\File-SynthesisOnly_StrTbl
...............................................\........\...\...\............\...................\Library-SynthesisOnly
...............................................\........\...\...\............\...................\Library-SynthesisOnly_StrTbl
...............................................\........\...\...\............\...................\Process-BehavioralSim-
...............................................\........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG
...............................................\........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG_StrTbl
...............................................\........\...\...\............\...................\Process-BehavioralSim-_StrTbl
...............................................\........\...\...\............\...................\Process-SynthesisOnly-
...............................................\........\...\...\............\...................\Process-SynthesisOnly-DESUT_UCF
...............................................\........\...\...\............\...................\Process-SynthesisOnly-DESUT_UCF_StrTbl
...............................................\........\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG
...............................................\........\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG_StrTbl
...............................................\........\...\...\............\...................\Process-SynthesisOnly-_StrTbl
...............................................\........\...\...\............\...................\Source-BehavioralSim-AutoCompile
...............................................\........\...\...\............\...................\Source-BehavioralSim-AutoCompile_StrTbl
...............................................\........\...\...\............\...................\Source-SynthesisOnly-AutoCompile
...............................................\........\...\...\............\...................\Source-SynthesisOnly-AutoCompile_StrTbl
...............................................\........\...\...\............\xreport\Gc_RvReportViewer-Current-Module
...............................................\........\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl
...............................................\........\..