文件名称:generic_fifo_yh
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Generic, multi-purpose FIFOs. Available as single clock and dual clock version, binary, lfsr, and gray encoded (dual clock only). All are parameterizable and use generic_memories for memory. These FIFOs are fully portable from FPGAs to ASICS.
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下载文件列表
generic_fifo_yh\tags\start\doc\README.txt
...............\....\.....\sim\rtl_sim\run\waves\waves.do
...............\....\.....\...\.......\bin\Makefile
...............\....\.....\bench\verilog\test_bench_top.v
...............\....\.....\rtl\verilog\timescale.v
...............\....\.....\...\.......\generic_fifo_dc.v
...............\....\.....\...\.......\generic_fifo_sc_b.v
...............\....\.....\...\.......\generic_fifo_sc_a.v
...............\.runk\doc\README.txt
...............\.....\sim\rtl_sim\run\waves\waves.do
...............\.....\...\.......\bin\Makefile
...............\.....\bench\verilog\test_bench_top.v
...............\.....\rtl\verilog\timescale.v
...............\.....\...\.......\lfsr.v
...............\.....\...\.......\generic_fifo_dc.v
...............\.....\...\.......\generic_fifo_lfsr.v
...............\.....\...\.......\generic_fifo_sc_b.v
...............\.....\...\.......\generic_fifo_sc_a.v
...............\.....\...\.......\generic_fifo_dc_gray.v
...............\.ags\start\sim\rtl_sim\run\waves
...............\....\.....\...\.......\run
...............\....\.....\...\.......\bin
...............\.runk\sim\rtl_sim\run\waves
...............\.ags\start\sim\rtl_sim
...............\....\.....\bench\verilog
...............\....\.....\rtl\verilog
...............\.runk\sim\rtl_sim\run
...............\.....\...\.......\bin
...............\.ags\start\doc
...............\....\.....\sim
...............\....\.....\bench
...............\....\.....\rtl
...............\.runk\sim\rtl_sim
...............\.....\bench\verilog
...............\.....\rtl\verilog
...............\.ags\start
...............\.runk\doc
...............\.....\sim
...............\.....\bench
...............\.....\rtl
...............\tags
...............\branches
...............\trunk
...............\web_uploads
generic_fifo_yh
...............\....\.....\sim\rtl_sim\run\waves\waves.do
...............\....\.....\...\.......\bin\Makefile
...............\....\.....\bench\verilog\test_bench_top.v
...............\....\.....\rtl\verilog\timescale.v
...............\....\.....\...\.......\generic_fifo_dc.v
...............\....\.....\...\.......\generic_fifo_sc_b.v
...............\....\.....\...\.......\generic_fifo_sc_a.v
...............\.runk\doc\README.txt
...............\.....\sim\rtl_sim\run\waves\waves.do
...............\.....\...\.......\bin\Makefile
...............\.....\bench\verilog\test_bench_top.v
...............\.....\rtl\verilog\timescale.v
...............\.....\...\.......\lfsr.v
...............\.....\...\.......\generic_fifo_dc.v
...............\.....\...\.......\generic_fifo_lfsr.v
...............\.....\...\.......\generic_fifo_sc_b.v
...............\.....\...\.......\generic_fifo_sc_a.v
...............\.....\...\.......\generic_fifo_dc_gray.v
...............\.ags\start\sim\rtl_sim\run\waves
...............\....\.....\...\.......\run
...............\....\.....\...\.......\bin
...............\.runk\sim\rtl_sim\run\waves
...............\.ags\start\sim\rtl_sim
...............\....\.....\bench\verilog
...............\....\.....\rtl\verilog
...............\.runk\sim\rtl_sim\run
...............\.....\...\.......\bin
...............\.ags\start\doc
...............\....\.....\sim
...............\....\.....\bench
...............\....\.....\rtl
...............\.runk\sim\rtl_sim
...............\.....\bench\verilog
...............\.....\rtl\verilog
...............\.ags\start
...............\.runk\doc
...............\.....\sim
...............\.....\bench
...............\.....\rtl
...............\tags
...............\branches
...............\trunk
...............\web_uploads
generic_fifo_yh