文件名称:Program6
介绍说明－－下载内容均来自于网络，请自行研究使用
用 vhdl 设计含异步清零和同步时钟使能的十进制加法计数器。再用 vhdl 设计含异步清零和同步时钟使能的十进制加减可控计数器。
-With vhdl design with asynchronous clear and synchronous clock enable decimal up counter. Vhdl design and then synchronize with asynchronous clear and clock enable control counter decimal addition and subtraction.
-With vhdl design with asynchronous clear and synchronous clock enable decimal up counter. Vhdl design and then synchronize with asynchronous clear and clock enable control counter decimal addition and subtraction.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Program6.txt