文件名称:design217
介绍说明－－下载内容均来自于网络，请自行研究使用
在quartus II中实现的一段分频代码，具有很好的使用价值，希望大家能够更好的借鉴。-FW FWKPJF F WJL FW FEL,M FW,M GERWELJ GEW RMGLEJWR4E GER ER FL OFE RGFE GRE GRTE GTRE 4ER OT EWWQO .
(系统自动生成,下载前可以参看下载内容)
下载文件列表
design217\clk_div.bsf
.........\clk_div.v
.........\clk_div.v.bak
.........\COUNT4.bsf
.........\design.asm.rpt
.........\design.bdf
.........\design.done
.........\design.eda.rpt
.........\design.fit.rpt
.........\design.fit.smsg
.........\design.fit.summary
.........\design.flow.rpt
.........\design.map.rpt
.........\design.map.summary
.........\design.pin
.........\design.pof
.........\design.qpf
.........\design.qsf
.........\design.qws
.........\design.sof
.........\design.tan.rpt
.........\design.v.bak
.........\design_nativelink_simulation.rpt
.........\plusegen.bsf
.........\plusegen.v
.........\plusegen.v.bak
.........\simulation\modelsim\design.sft
.........\..........\........\design.vo
.........\..........\........\design.vt
.........\..........\........\design_modelsim.xrf
.........\..........\........\design_run_msim_rtl_verilog.do
.........\..........\........\design_run_msim_rtl_verilog.do.bak
.........\..........\........\design_v.sdo
.........\..........\........\modelsim.ini
.........\..........\........\msim_transcript
.........\..........\........\rtl_work\_info
.........\..........\........\........\_vmake
.........\..........\........\........\.temp\vlog1t1sjw
.........\..........\........\........\.....\vlog76kevr
.........\..........\........\........\plusegen\verilog.prw
.........\..........\........\........\........\verilog.psm
.........\..........\........\........\........\_primary.dat
.........\..........\........\........\........\_primary.dbs
.........\..........\........\........\........\_primary.vhd
.........\..........\........\........\clk_div\verilog.prw
.........\..........\........\........\.......\verilog.psm
.........\..........\........\........\.......\_primary.dat
.........\..........\........\........\.......\_primary.dbs
.........\..........\........\........\.......\_primary.vhd
.........\..........\........\........\@c@o@u@n@t4\verilog.prw
.........\..........\........\........\...........\verilog.psm
.........\..........\........\........\...........\_primary.dat
.........\..........\........\........\...........\_primary.dbs
.........\..........\........\........\...........\_primary.vhd
.........\incremental_db\README
.........\..............\compiled_partitions\design.root_partition.cmp.cdb
.........\..............\...................\design.root_partition.cmp.dfp
.........\..............\...................\design.root_partition.cmp.hdb
.........\..............\...................\design.root_partition.cmp.kpt
.........\..............\...................\design.root_partition.cmp.logdb
.........\..............\...................\design.root_partition.cmp.rcfdb
.........\..............\...................\design.root_partition.cmp.re.rcfdb
.........\..............\...................\design.root_partition.map.cdb
.........\..............\...................\design.root_partition.map.dpi
.........\..............\...................\design.root_partition.map.hdb
.........\..............\...................\design.root_partition.map.kpt
.........\db\design.asm.qmsg
.........\..\design.asm.rdb
.........\..\design.asm_labs.ddb
.........\..\design.cbx.xml
.........\..\design.cmp.bpm
.........\..\design.cmp.cdb
.........\..\design.cmp.ecobp
.........\..\design.cmp.hdb
.........\..\design.cmp.kpt
.........\..\design.cmp.logdb
.........\..\design.cmp.rdb
.........\..\design.cmp.tdb
.........\..\design.cmp0.ddb
.........\..\design.cmp2.ddb
.........\..\design.cmp_merge.kpt
.........\..\design.db_info
.........\..\design.eco.cdb
.........\..\design.eda.qmsg
.........\..\design.fit.qmsg
.........\..\design.hier_info
.........\..\design.hif
.........\..\design.lpc.html
.........\..\design.lpc.rdb
.........\..\design.lpc.txt
.........\..\design.map.bpm
.........\..\design.map.cdb
.........\..\design.map.ecobp
.........\..\design.map.hdb
.........\..\design.map.kpt
.........\..\design.map.logdb
.........\..\design.map.qmsg
.........\..\design.map_bb.cdb
.........\..\design.map_bb.hdb
.........\..\design.map_bb.logdb
.........\clk_div.v
.........\clk_div.v.bak
.........\COUNT4.bsf
.........\design.asm.rpt
.........\design.bdf
.........\design.done
.........\design.eda.rpt
.........\design.fit.rpt
.........\design.fit.smsg
.........\design.fit.summary
.........\design.flow.rpt
.........\design.map.rpt
.........\design.map.summary
.........\design.pin
.........\design.pof
.........\design.qpf
.........\design.qsf
.........\design.qws
.........\design.sof
.........\design.tan.rpt
.........\design.v.bak
.........\design_nativelink_simulation.rpt
.........\plusegen.bsf
.........\plusegen.v
.........\plusegen.v.bak
.........\simulation\modelsim\design.sft
.........\..........\........\design.vo
.........\..........\........\design.vt
.........\..........\........\design_modelsim.xrf
.........\..........\........\design_run_msim_rtl_verilog.do
.........\..........\........\design_run_msim_rtl_verilog.do.bak
.........\..........\........\design_v.sdo
.........\..........\........\modelsim.ini
.........\..........\........\msim_transcript
.........\..........\........\rtl_work\_info
.........\..........\........\........\_vmake
.........\..........\........\........\.temp\vlog1t1sjw
.........\..........\........\........\.....\vlog76kevr
.........\..........\........\........\plusegen\verilog.prw
.........\..........\........\........\........\verilog.psm
.........\..........\........\........\........\_primary.dat
.........\..........\........\........\........\_primary.dbs
.........\..........\........\........\........\_primary.vhd
.........\..........\........\........\clk_div\verilog.prw
.........\..........\........\........\.......\verilog.psm
.........\..........\........\........\.......\_primary.dat
.........\..........\........\........\.......\_primary.dbs
.........\..........\........\........\.......\_primary.vhd
.........\..........\........\........\@c@o@u@n@t4\verilog.prw
.........\..........\........\........\...........\verilog.psm
.........\..........\........\........\...........\_primary.dat
.........\..........\........\........\...........\_primary.dbs
.........\..........\........\........\...........\_primary.vhd
.........\incremental_db\README
.........\..............\compiled_partitions\design.root_partition.cmp.cdb
.........\..............\...................\design.root_partition.cmp.dfp
.........\..............\...................\design.root_partition.cmp.hdb
.........\..............\...................\design.root_partition.cmp.kpt
.........\..............\...................\design.root_partition.cmp.logdb
.........\..............\...................\design.root_partition.cmp.rcfdb
.........\..............\...................\design.root_partition.cmp.re.rcfdb
.........\..............\...................\design.root_partition.map.cdb
.........\..............\...................\design.root_partition.map.dpi
.........\..............\...................\design.root_partition.map.hdb
.........\..............\...................\design.root_partition.map.kpt
.........\db\design.asm.qmsg
.........\..\design.asm.rdb
.........\..\design.asm_labs.ddb
.........\..\design.cbx.xml
.........\..\design.cmp.bpm
.........\..\design.cmp.cdb
.........\..\design.cmp.ecobp
.........\..\design.cmp.hdb
.........\..\design.cmp.kpt
.........\..\design.cmp.logdb
.........\..\design.cmp.rdb
.........\..\design.cmp.tdb
.........\..\design.cmp0.ddb
.........\..\design.cmp2.ddb
.........\..\design.cmp_merge.kpt
.........\..\design.db_info
.........\..\design.eco.cdb
.........\..\design.eda.qmsg
.........\..\design.fit.qmsg
.........\..\design.hier_info
.........\..\design.hif
.........\..\design.lpc.html
.........\..\design.lpc.rdb
.........\..\design.lpc.txt
.........\..\design.map.bpm
.........\..\design.map.cdb
.........\..\design.map.ecobp
.........\..\design.map.hdb
.........\..\design.map.kpt
.........\..\design.map.logdb
.........\..\design.map.qmsg
.........\..\design.map_bb.cdb
.........\..\design.map_bb.hdb
.........\..\design.map_bb.logdb