文件名称:2259647AlteraSDR-SDRAM
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Summary: InterPreTS (Interaction Prediction through Tertiary Structure) is a web-based version of our method for predicting protein-protein interactions (Aloy and Russell, 2002, Proc. Natl Acad. Sci. USA, 99, 5896-5901). Given a pair of query sequences, we first search for homologues in a database of interacting domains (DBID) of known three-dimensional complex structures. Pairs of sequences homologous to a known interacting
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下载文件列表
2259647Al''teraSDR-SDRAM\doc\readme.txt
........................\...\sdr_sdram.pdf
........................\model\mt48lc8m16a2.v
........................\route\PLL1.v
........................\.....\sdr_sdram.csf
........................\.....\sdr_sdram.esf
........................\.....\sdr_sdram.vqm
........................\simulation\modelsim.ini
........................\..........\readme.txt
........................\..........\sdr_sdram_tb.v
........................\..........\work\altclklock\verilog.psm
........................\..........\....\..........\_primary.dat
........................\..........\....\..........\_primary.vhd
........................\..........\....\command\verilog.psm
........................\..........\....\.......\_primary.dat
........................\..........\....\.......\_primary.vhd
........................\..........\....\..ntrol_interface\verilog.psm
........................\..........\....\.................\_primary.dat
........................\..........\....\.................\_primary.vhd
........................\..........\....\mt48lc8m16a2\verilog.psm
........................\..........\....\............\_primary.dat
........................\..........\....\............\_primary.vhd
........................\..........\....\pll1\verilog.psm
........................\..........\....\....\_primary.dat
........................\..........\....\....\_primary.vhd
........................\..........\....\sdr_data_path\verilog.psm
........................\..........\....\.............\_primary.dat
........................\..........\....\.............\_primary.vhd
........................\..........\....\....sdram\verilog.psm
........................\..........\....\.........\_primary.dat
........................\..........\....\.........\_primary.vhd
........................\..........\....\........._tb\verilog.psm
........................\..........\....\............\_primary.dat
........................\..........\....\............\_primary.vhd
........................\..........\....\_info
........................\.ource\altclklock.v
........................\......\Command.v
........................\......\compile_all.v
........................\......\control_interface.v
........................\......\Params.v
........................\......\PLL1.v
........................\......\sdr_data_path.v
........................\......\sdr_sdram.v
........................\.ynthesis\synplicity\sdr_sdram.prj
........................\.imulation\work\altclklock
........................\..........\....\command
........................\..........\....\control_interface
........................\..........\....\mt48lc8m16a2
........................\..........\....\pll1
........................\..........\....\sdr_data_path
........................\..........\....\sdr_sdram
........................\..........\....\sdr_sdram_tb
........................\..........\work
........................\.ynthesis\synplicity
........................\doc
........................\model
........................\route
........................\simulation
........................\source
........................\synthesis
2259647Al''teraSDR-SDRAM
........................\...\sdr_sdram.pdf
........................\model\mt48lc8m16a2.v
........................\route\PLL1.v
........................\.....\sdr_sdram.csf
........................\.....\sdr_sdram.esf
........................\.....\sdr_sdram.vqm
........................\simulation\modelsim.ini
........................\..........\readme.txt
........................\..........\sdr_sdram_tb.v
........................\..........\work\altclklock\verilog.psm
........................\..........\....\..........\_primary.dat
........................\..........\....\..........\_primary.vhd
........................\..........\....\command\verilog.psm
........................\..........\....\.......\_primary.dat
........................\..........\....\.......\_primary.vhd
........................\..........\....\..ntrol_interface\verilog.psm
........................\..........\....\.................\_primary.dat
........................\..........\....\.................\_primary.vhd
........................\..........\....\mt48lc8m16a2\verilog.psm
........................\..........\....\............\_primary.dat
........................\..........\....\............\_primary.vhd
........................\..........\....\pll1\verilog.psm
........................\..........\....\....\_primary.dat
........................\..........\....\....\_primary.vhd
........................\..........\....\sdr_data_path\verilog.psm
........................\..........\....\.............\_primary.dat
........................\..........\....\.............\_primary.vhd
........................\..........\....\....sdram\verilog.psm
........................\..........\....\.........\_primary.dat
........................\..........\....\.........\_primary.vhd
........................\..........\....\........._tb\verilog.psm
........................\..........\....\............\_primary.dat
........................\..........\....\............\_primary.vhd
........................\..........\....\_info
........................\.ource\altclklock.v
........................\......\Command.v
........................\......\compile_all.v
........................\......\control_interface.v
........................\......\Params.v
........................\......\PLL1.v
........................\......\sdr_data_path.v
........................\......\sdr_sdram.v
........................\.ynthesis\synplicity\sdr_sdram.prj
........................\.imulation\work\altclklock
........................\..........\....\command
........................\..........\....\control_interface
........................\..........\....\mt48lc8m16a2
........................\..........\....\pll1
........................\..........\....\sdr_data_path
........................\..........\....\sdr_sdram
........................\..........\....\sdr_sdram_tb
........................\..........\work
........................\.ynthesis\synplicity
........................\doc
........................\model
........................\route
........................\simulation
........................\source
........................\synthesis
2259647Al''teraSDR-SDRAM