文件名称:Altium-Designer-Summer-09-
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Altium Designer Summer 09 源文件：大量的实用电路图以及印制电路板-Altium Designer Summer 09 source files： a large number of practical circuit diagram and printed circuit boards
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下载文件列表
Altium Designer Summer 09源文件\第10章 可编程逻辑器件\10.2\16Bit Counter.SchDoc
...............................\.....................\....\16Bit Counter.SchDocPreview
...............................\.....................\....\FPGA_16BitCounter.PrjFpg
...............................\.....................\....\FPGA_16BitCounter.PrjFpgStructure
...............................\.....................\....\ProjectOutputs\16Bit Counter.VHD
...............................\.....................\....\..............\16Bit Counter.VHDPreview
...............................\.....................\....\..............\FPGA_16BitCounter.EDF
...............................\.....................\....\..............\FPGA_16BitCounter.EDFPreview
...............................\.....................\....\..............\Status Report.Txt
...............................\.....................\...5\BCD.VHD
...............................\.....................\....\BCD.VHDPreview
...............................\.....................\....\BCD8.PrjFpg
...............................\.....................\....\BCD8.PrjFpgStructure
...............................\.....................\....\BCD8.schdoc
...............................\.....................\....\BCD8.schdocPreview
...............................\.....................\....\BCD8.SO
...............................\.....................\....\BCD8.VHD
...............................\.....................\....\BCD8.VHDPreview
...............................\.....................\....\Bufgs.vhd
...............................\.....................\....\Bufgs.vhdPreview
...............................\.....................\....\History\32FB62B7\BCD_LIB.~(1).VHDLIB.Zip
...............................\.....................\....\.......\80EE16AB\Bcd.~(1).schlib.Zip
...............................\.....................\....\.......\BCD8.~(1).PrjFpg.Zip
...............................\.....................\....\.......\BCD8.~(3).PrjFpg.Zip
...............................\.....................\....\Out\BCD.VHD
...............................\.....................\....\...\BCD.VHDPreview
...............................\.....................\....\...\BCD8.VHD
...............................\.....................\....\Parity.vhd
...............................\.....................\....\Parity.vhdPreview
...............................\.....................\....\SCH Library\Bcd.schlib
...............................\.....................\....\TestBCD.VHDTST
...............................\.....................\....\TestBCD.VHDTSTPreview
...............................\.....................\....\Utility.vhd
...............................\.....................\....\Utility.vhdPreview
...............................\.....................\....\VHDL Library\BCD_LIB.AL
...............................\.....................\....\............\BCD_LIB.VHDLIB
...............................\.....................\....\............\BUFGS.AN
...............................\.....................\....\............\Bufgs.vhd
...............................\.....................\....\............\Bufgs.vhdPreview
...............................\.....................\....\............\PARITY.AN
...............................\.....................\....\............\Parity.vhd
...............................\.....................\....\............\Parity.vhdPreview
...............................\.....................\....\............\UTILITY.AN
...............................\.....................\....\............\Utility.vhd
...............................\.....................\....\............\Utility.vhdPreview
...............................\.....................\上机实验\实验1\History\Test1.~(1).PrjFpg.Zip
...............................\.....................\........\.....\ProjectOutputs\Status Report.Txt
...............................\.....................\........\.....\..............\Test1.EDF
...............................\.....................\........\.....\..............\Test1.EDFPreview
.................
...............................\.....................\....\16Bit Counter.SchDocPreview
...............................\.....................\....\FPGA_16BitCounter.PrjFpg
...............................\.....................\....\FPGA_16BitCounter.PrjFpgStructure
...............................\.....................\....\ProjectOutputs\16Bit Counter.VHD
...............................\.....................\....\..............\16Bit Counter.VHDPreview
...............................\.....................\....\..............\FPGA_16BitCounter.EDF
...............................\.....................\....\..............\FPGA_16BitCounter.EDFPreview
...............................\.....................\....\..............\Status Report.Txt
...............................\.....................\...5\BCD.VHD
...............................\.....................\....\BCD.VHDPreview
...............................\.....................\....\BCD8.PrjFpg
...............................\.....................\....\BCD8.PrjFpgStructure
...............................\.....................\....\BCD8.schdoc
...............................\.....................\....\BCD8.schdocPreview
...............................\.....................\....\BCD8.SO
...............................\.....................\....\BCD8.VHD
...............................\.....................\....\BCD8.VHDPreview
...............................\.....................\....\Bufgs.vhd
...............................\.....................\....\Bufgs.vhdPreview
...............................\.....................\....\History\32FB62B7\BCD_LIB.~(1).VHDLIB.Zip
...............................\.....................\....\.......\80EE16AB\Bcd.~(1).schlib.Zip
...............................\.....................\....\.......\BCD8.~(1).PrjFpg.Zip
...............................\.....................\....\.......\BCD8.~(3).PrjFpg.Zip
...............................\.....................\....\Out\BCD.VHD
...............................\.....................\....\...\BCD.VHDPreview
...............................\.....................\....\...\BCD8.VHD
...............................\.....................\....\Parity.vhd
...............................\.....................\....\Parity.vhdPreview
...............................\.....................\....\SCH Library\Bcd.schlib
...............................\.....................\....\TestBCD.VHDTST
...............................\.....................\....\TestBCD.VHDTSTPreview
...............................\.....................\....\Utility.vhd
...............................\.....................\....\Utility.vhdPreview
...............................\.....................\....\VHDL Library\BCD_LIB.AL
...............................\.....................\....\............\BCD_LIB.VHDLIB
...............................\.....................\....\............\BUFGS.AN
...............................\.....................\....\............\Bufgs.vhd
...............................\.....................\....\............\Bufgs.vhdPreview
...............................\.....................\....\............\PARITY.AN
...............................\.....................\....\............\Parity.vhd
...............................\.....................\....\............\Parity.vhdPreview
...............................\.....................\....\............\UTILITY.AN
...............................\.....................\....\............\Utility.vhd
...............................\.....................\....\............\Utility.vhdPreview
...............................\.....................\上机实验\实验1\History\Test1.~(1).PrjFpg.Zip
...............................\.....................\........\.....\ProjectOutputs\Status Report.Txt
...............................\.....................\........\.....\..............\Test1.EDF
...............................\.....................\........\.....\..............\Test1.EDFPreview
.................