文件名称:31241213verilog_uart_NO
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FPGA串口通讯例程，经我修改绝对可用； 默认48M,9600-8-1/2，如果时钟不同只需修改时钟分频数即可。-The FPGA serial interface communication by the modified routine, absolute can be used The default 48 M, 9600-8-1/2, if the clock different modify it only clock points frequency can.
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下载文件列表
uart\smartgen\smartgen.aws
....\hdl\speed_select.v
....\...\my_uart_tx.v
....\...\my_uart_top.v
....\...\my_uart_rx.v
....\viewdraw\vf\project.lst
....\........\viewdraw.ini
....\simulation\modelsim.ini.sav
....\..........\modelsim.ini
....\.ynthesis\stdout.log
....\.........\.yntmp\sap.log
....\.........\......\my_uart_top.plg
....\.........\backup\my_uart_top.srr
....\.........\run_options.txt
....\.........\my_uart_top.tlg
....\.........\my_uart_top.sap
....\.........\my_uart_top.fse
....\.........\my_uart_top.szr
....\.........\traplog.tlg
....\.........\.recordref
....\.........\my_uart_top.srd
....\.........\my_uart_top.srm
....\.........\my_uart_top.map
....\.........\my_uart_top.edn
....\.........\my_uart_top.sdf
....\.........\my_uart_top.pdc
....\.........\my_uart_top_sdc.sdc
....\.........\my_uart_top.so
....\.........\my_uart_top.areasrr
....\.........\my_uart_top_syn.prj
....\.........\my_uart_top.srr
....\.........\my_uart_top.srs
....\designer\impl1\my_uart_top.ide_des
....\........\.....\my_uart_rx.ide_des
....\........\.....\speed_select.ide_des
....\........\.....\my_uart_top.tcl
....\........\.....\............dtf\verify.log
....\........\.....\my_uart_top.pdb
....\........\.....\my_uart_top.pdb.depends
....\........\.....\designer.log
....\........\.....\my_uart_top_fp\my_uart_top.pro
....\........\.....\..............\$$FlashPro_FPBBALTLPT1.L$$
....\........\.....\..............\projectData\my_uart_top.pdb
....\........\.....\..............\my_uart_top.log
....\........\.....\my_uart_tx.ide_des
....\........\.....\my_uart_top.adb
....\uart.prj
....\designer\impl1\my_uart_top_fp\projectData
....\........\.....\simulation
....\........\.....\my_uart_top.dtf
....\........\.....\my_uart_top_fp
....\viewdraw\vf
....\........\sch
....\........\sym
....\........\wir
....\synthesis\syntmp
....\.........\coreip
....\.........\backup
....\designer\impl1
....\smartgen
....\hdl
....\constraint
....\viewdraw
....\component
....\coreconsole
....\simulation
....\synthesis
....\phy_synthesis
....\stimulus
....\designer
uart
....\hdl\speed_select.v
....\...\my_uart_tx.v
....\...\my_uart_top.v
....\...\my_uart_rx.v
....\viewdraw\vf\project.lst
....\........\viewdraw.ini
....\simulation\modelsim.ini.sav
....\..........\modelsim.ini
....\.ynthesis\stdout.log
....\.........\.yntmp\sap.log
....\.........\......\my_uart_top.plg
....\.........\backup\my_uart_top.srr
....\.........\run_options.txt
....\.........\my_uart_top.tlg
....\.........\my_uart_top.sap
....\.........\my_uart_top.fse
....\.........\my_uart_top.szr
....\.........\traplog.tlg
....\.........\.recordref
....\.........\my_uart_top.srd
....\.........\my_uart_top.srm
....\.........\my_uart_top.map
....\.........\my_uart_top.edn
....\.........\my_uart_top.sdf
....\.........\my_uart_top.pdc
....\.........\my_uart_top_sdc.sdc
....\.........\my_uart_top.so
....\.........\my_uart_top.areasrr
....\.........\my_uart_top_syn.prj
....\.........\my_uart_top.srr
....\.........\my_uart_top.srs
....\designer\impl1\my_uart_top.ide_des
....\........\.....\my_uart_rx.ide_des
....\........\.....\speed_select.ide_des
....\........\.....\my_uart_top.tcl
....\........\.....\............dtf\verify.log
....\........\.....\my_uart_top.pdb
....\........\.....\my_uart_top.pdb.depends
....\........\.....\designer.log
....\........\.....\my_uart_top_fp\my_uart_top.pro
....\........\.....\..............\$$FlashPro_FPBBALTLPT1.L$$
....\........\.....\..............\projectData\my_uart_top.pdb
....\........\.....\..............\my_uart_top.log
....\........\.....\my_uart_tx.ide_des
....\........\.....\my_uart_top.adb
....\uart.prj
....\designer\impl1\my_uart_top_fp\projectData
....\........\.....\simulation
....\........\.....\my_uart_top.dtf
....\........\.....\my_uart_top_fp
....\viewdraw\vf
....\........\sch
....\........\sym
....\........\wir
....\synthesis\syntmp
....\.........\coreip
....\.........\backup
....\designer\impl1
....\smartgen
....\hdl
....\constraint
....\viewdraw
....\component
....\coreconsole
....\simulation
....\synthesis
....\phy_synthesis
....\stimulus
....\designer
uart