文件名称:SDR_SDRAM_IP

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [PDF]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 2.25mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • peter*****
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SDR SDRAM 控制器,Altera官网重要资料。内涵说明文档,和VHDL与Verilog两种设计IP。-SDR SDRAM controller from Altera
相关搜索: sdr_sdram
sdr
sdram
ip

(系统自动生成,下载前可以参看下载内容)

下载文件列表

SDR_SDRAM_IP\sdr_sdram.pdf

............\verilog\doc\readme.txt

............\.......\...\sdr_sdram.pdf

............\.......\model\mt48lc8m16a2.v

............\.......\route\PLL1.v

............\.......\.....\sdr_sdram.csf

............\.......\.....\sdr_sdram.esf

............\.......\.....\sdr_sdram.vqm

............\.......\simulation\modelsim.ini

............\.......\..........\readme.txt

............\.......\..........\sdr_sdram_tb.v

............\.......\..........\work\altclklock\verilog.psm

............\.......\..........\....\..........\_primary.dat

............\.......\..........\....\..........\_primary.vhd

............\.......\..........\....\command\verilog.psm

............\.......\..........\....\.......\_primary.dat

............\.......\..........\....\.......\_primary.vhd

............\.......\..........\....\..ntrol_interface\verilog.psm

............\.......\..........\....\.................\_primary.dat

............\.......\..........\....\.................\_primary.vhd

............\.......\..........\....\mt48lc8m16a2\verilog.psm

............\.......\..........\....\............\_primary.dat

............\.......\..........\....\............\_primary.vhd

............\.......\..........\....\pll1\verilog.psm

............\.......\..........\....\....\_primary.dat

............\.......\..........\....\....\_primary.vhd

............\.......\..........\....\sdr_data_path\verilog.psm

............\.......\..........\....\.............\_primary.dat

............\.......\..........\....\.............\_primary.vhd

............\.......\..........\....\....sdram\verilog.psm

............\.......\..........\....\.........\_primary.dat

............\.......\..........\....\.........\_primary.vhd

............\.......\..........\....\........._tb\verilog.psm

............\.......\..........\....\............\_primary.dat

............\.......\..........\....\............\_primary.vhd

............\.......\..........\....\_info

............\.......\.ource\altclklock.v

............\.......\......\Command.v

............\.......\......\compile_all.v

............\.......\......\control_interface.v

............\.......\......\Params.v

............\.......\......\PLL1.v

............\.......\......\sdr_data_path.v

............\.......\......\sdr_sdram.v

............\.......\.ynthesis\synplicity\sdr_sdram.prj

............\.hdl\doc\readme.txt

............\....\...\sdr_sdram.pdf

............\....\model\io_utils.vhd

............\....\.....\mt48lc8m16a2.vhd

............\....\.....\mt48lc8m16a2.zip

............\....\.....\mti_pkg.vhd

............\....\.....\stdlogar.vhd

............\....\.....\util1164.vhd

............\....\route\pll1.vhd

............\....\.....\sdr_sdram.csf

............\....\.....\sdr_sdram.esf

............\....\.....\sdr_sdram.vqm

............\....\simulation\APEX20KE_MF.VHD

............\....\..........\io_utils.vhd

............\....\..........\lpm_pack.vhd

............\....\..........\modelsim.ini

............\....\..........\mt48lc8m16a2.vhd

............\....\..........\mti_pkg.vhd

............\....\..........\readme.txt

............\....\..........\sdr_sdram_tb.vhd

............\....\..........\stdlogar.vhd

............\....\..........\util1164.vhd

............\....\..........\work\altcam\behave.dat

............\....\..........\....\......\behave.psm

............\....\..........\....\......\_primary.dat

............\....\..........\....\....lklock\behavior.dat

............\....\..........\....\..........\behavior.psm

............\....\..........\....\..........\_primary.dat

............\....\..........\....\...lvds_rx\behavior.dat

............\....\..........\....\..........\behavior.psm

............\....\..........\....\..........\_primary.dat

............\....\..........\....\........tx\behavior.dat

............\....\..........\....\..........\behavior.psm

............\....\..........\....\..........\_primary.dat

............\....\..........\....\command\rtl.dat

............\....\..........\....\.......\rtl.psm

............\....\..........\....\.......\_primary.dat

............\....\..........\....\..ntrol_interface\rtl.dat

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