文件名称:VGA_CTL
介绍说明－－下载内容均来自于网络，请自行研究使用
通过VGA显示一个汉字，用verilog编写，属于进阶实验-Through a VGA display Chinese characters, written with verilog, are advanced experimental
(系统自动生成,下载前可以参看下载内容)
下载文件列表
VGA_CTL\Testbench\altera_mf.v
.......\.........\VGA_tb.v
.......\src\.VGA_CTL.v.swp
.......\...\ROM.v
.......\...\VGA_CHINESE_HONG.mif
.......\...\VGA_CTL.v
.......\Quartus\VGA_CTL.asm.rpt
.......\.......\VGA_CTL.done
.......\.......\VGA_CTL.dpf
.......\.......\VGA_CTL.fit.rpt
.......\.......\VGA_CTL.fit.smsg
.......\.......\VGA_CTL.fit.summary
.......\.......\VGA_CTL.flow.rpt
.......\.......\VGA_CTL.map.rpt
.......\.......\VGA_CTL.map.summary
.......\.......\VGA_CTL.pin
.......\.......\VGA_CTL.pof
.......\.......\VGA_CTL.qpf
.......\.......\VGA_CTL.qsf
.......\.......\VGA_CTL.qws
.......\.......\VGA_CTL.sof
.......\.......\VGA_CTL.tan.rpt
.......\.......\VGA_CTL.tan.summary
.......\.......\incremental_db\README
.......\.......\..............\compiled_partitions\VGA_CTL.root_partition.cmp.atm
.......\.......\..............\...................\VGA_CTL.root_partition.cmp.dfp
.......\.......\..............\...................\VGA_CTL.root_partition.cmp.hdbx
.......\.......\..............\...................\VGA_CTL.root_partition.cmp.kpt
.......\.......\..............\...................\VGA_CTL.root_partition.cmp.logdb
.......\.......\..............\...................\VGA_CTL.root_partition.cmp.rcf
.......\.......\..............\...................\VGA_CTL.root_partition.map.atm
.......\.......\..............\...................\VGA_CTL.root_partition.map.dpi
.......\.......\..............\...................\VGA_CTL.root_partition.map.hdbx
.......\.......\..............\...................\VGA_CTL.root_partition.map.kpt
.......\.......\db\altsyncram_3881.tdf
.......\.......\..\prev_cmp_VGA_CTL.asm.qmsg
.......\.......\..\prev_cmp_VGA_CTL.fit.qmsg
.......\.......\..\prev_cmp_VGA_CTL.map.qmsg
.......\.......\..\prev_cmp_VGA_CTL.qmsg
.......\.......\..\prev_cmp_VGA_CTL.tan.qmsg
.......\.......\..\VGA.db_info
.......\.......\..\VGA.eco.cdb
.......\.......\..\VGA.sld_design_entry.sci
.......\.......\..\VGA_CTL.db_info
.......\.......\..\VGA_CTL.eco.cdb
.......\.......\..\VGA_CTL.sld_design_entry.sci
.......\.......\..\VGA_CTL_global_asgn_op.abo
.......\modelsim\transcript
.......\........\VGA.cr.mti
.......\........\vga.do
.......\........\VGA.mpf
.......\........\vsim.wlf
.......\........\work\_info
.......\........\....\ttn_scale_cntr\_primary.dat
.......\........\....\..............\_primary.vhd
.......\........\....\....n_cntr\_primary.dat
.......\........\....\..........\_primary.vhd
.......\........\....\....m_cntr\_primary.dat
.......\........\....\..........\_primary.vhd
.......\........\....\stx_scale_cntr\_primary.dat
.......\........\....\..............\_primary.vhd
.......\........\....\....n_cntr\_primary.dat
.......\........\....\..........\_primary.vhd
.......\........\....\....m_cntr\_primary.dat
.......\........\....\..........\_primary.vhd
.......\........\....\..ratix_tx_outclk\_primary.dat
.......\........\....\.................\_primary.vhd
.......\........\....\........lvds_rx\_primary.dat
.......\........\....\...............\_primary.vhd
.......\........\....\.......ii_tx_outclk\_primary.dat
.......\........\....\...................\_primary.vhd
.......\........\....\..........lvds_rx\_primary.dat
.......\........\....\.................\_primary.vhd
.......\........\....\.........i_lvds_rx_dpa\_primary.dat
.......\........\....\......................\_primary.vhd
.......\........\....\...................channel\_primary.dat
.......\........\....\..........................\_primary.vhd
.......\........\....\..................\_primary.dat
.......\........\....\..................\_primary.vhd
.......\........\....\.......gx_dpa_lvds_rx\_primary.dat
.......\........\....\.....................\_primary.vhd
.......\........\....\.ld_virtual_jtag\_primary.dat
.......\........\....\................\_primary.vhd
.......\........\....\....signaltap\_primary.dat
.......\........\....\.............\_primary.vhd
.......\........\....\.ignal_gen\_primary.dat
.......\........\....\..........\_primary.vhd
.......\........\....\.cfifo\_primary.dat
.......\........\....\......\_primary.vhd
.......\........\....\pll_iob
.......\.........\VGA_tb.v
.......\src\.VGA_CTL.v.swp
.......\...\ROM.v
.......\...\VGA_CHINESE_HONG.mif
.......\...\VGA_CTL.v
.......\Quartus\VGA_CTL.asm.rpt
.......\.......\VGA_CTL.done
.......\.......\VGA_CTL.dpf
.......\.......\VGA_CTL.fit.rpt
.......\.......\VGA_CTL.fit.smsg
.......\.......\VGA_CTL.fit.summary
.......\.......\VGA_CTL.flow.rpt
.......\.......\VGA_CTL.map.rpt
.......\.......\VGA_CTL.map.summary
.......\.......\VGA_CTL.pin
.......\.......\VGA_CTL.pof
.......\.......\VGA_CTL.qpf
.......\.......\VGA_CTL.qsf
.......\.......\VGA_CTL.qws
.......\.......\VGA_CTL.sof
.......\.......\VGA_CTL.tan.rpt
.......\.......\VGA_CTL.tan.summary
.......\.......\incremental_db\README
.......\.......\..............\compiled_partitions\VGA_CTL.root_partition.cmp.atm
.......\.......\..............\...................\VGA_CTL.root_partition.cmp.dfp
.......\.......\..............\...................\VGA_CTL.root_partition.cmp.hdbx
.......\.......\..............\...................\VGA_CTL.root_partition.cmp.kpt
.......\.......\..............\...................\VGA_CTL.root_partition.cmp.logdb
.......\.......\..............\...................\VGA_CTL.root_partition.cmp.rcf
.......\.......\..............\...................\VGA_CTL.root_partition.map.atm
.......\.......\..............\...................\VGA_CTL.root_partition.map.dpi
.......\.......\..............\...................\VGA_CTL.root_partition.map.hdbx
.......\.......\..............\...................\VGA_CTL.root_partition.map.kpt
.......\.......\db\altsyncram_3881.tdf
.......\.......\..\prev_cmp_VGA_CTL.asm.qmsg
.......\.......\..\prev_cmp_VGA_CTL.fit.qmsg
.......\.......\..\prev_cmp_VGA_CTL.map.qmsg
.......\.......\..\prev_cmp_VGA_CTL.qmsg
.......\.......\..\prev_cmp_VGA_CTL.tan.qmsg
.......\.......\..\VGA.db_info
.......\.......\..\VGA.eco.cdb
.......\.......\..\VGA.sld_design_entry.sci
.......\.......\..\VGA_CTL.db_info
.......\.......\..\VGA_CTL.eco.cdb
.......\.......\..\VGA_CTL.sld_design_entry.sci
.......\.......\..\VGA_CTL_global_asgn_op.abo
.......\modelsim\transcript
.......\........\VGA.cr.mti
.......\........\vga.do
.......\........\VGA.mpf
.......\........\vsim.wlf
.......\........\work\_info
.......\........\....\ttn_scale_cntr\_primary.dat
.......\........\....\..............\_primary.vhd
.......\........\....\....n_cntr\_primary.dat
.......\........\....\..........\_primary.vhd
.......\........\....\....m_cntr\_primary.dat
.......\........\....\..........\_primary.vhd
.......\........\....\stx_scale_cntr\_primary.dat
.......\........\....\..............\_primary.vhd
.......\........\....\....n_cntr\_primary.dat
.......\........\....\..........\_primary.vhd
.......\........\....\....m_cntr\_primary.dat
.......\........\....\..........\_primary.vhd
.......\........\....\..ratix_tx_outclk\_primary.dat
.......\........\....\.................\_primary.vhd
.......\........\....\........lvds_rx\_primary.dat
.......\........\....\...............\_primary.vhd
.......\........\....\.......ii_tx_outclk\_primary.dat
.......\........\....\...................\_primary.vhd
.......\........\....\..........lvds_rx\_primary.dat
.......\........\....\.................\_primary.vhd
.......\........\....\.........i_lvds_rx_dpa\_primary.dat
.......\........\....\......................\_primary.vhd
.......\........\....\...................channel\_primary.dat
.......\........\....\..........................\_primary.vhd
.......\........\....\..................\_primary.dat
.......\........\....\..................\_primary.vhd
.......\........\....\.......gx_dpa_lvds_rx\_primary.dat
.......\........\....\.....................\_primary.vhd
.......\........\....\.ld_virtual_jtag\_primary.dat
.......\........\....\................\_primary.vhd
.......\........\....\....signaltap\_primary.dat
.......\........\....\.............\_primary.vhd
.......\........\....\.ignal_gen\_primary.dat
.......\........\....\..........\_primary.vhd
.......\........\....\.cfifo\_primary.dat
.......\........\....\......\_primary.vhd
.......\........\....\pll_iob