文件名称:WASH
介绍说明－－下载内容均来自于网络，请自行研究使用
VHDL编写的模拟洗衣机程序，能正转20s，暂停10s，反转20s，暂停10s，可能设定要运行的初始时间！-Washing machine simulation program written in VHDL, can forward 20s, pause 10s, reverse 20s, pause 10s, may set the initial time to run!
(系统自动生成,下载前可以参看下载内容)
下载文件列表
WASH
....\BEEP.bsf
....\beep.vhd
....\counter.bsf
....\counter.vhd
....\db
....\..\top.asm.qmsg
....\..\top.cbx.xml
....\..\top.cmp.cdb
....\..\top.cmp.hdb
....\..\top.cmp.kpt
....\..\top.cmp.logdb
....\..\top.cmp.rdb
....\..\top.cmp.tdb
....\..\top.cmp0.ddb
....\..\top.dbp
....\..\top.db_info
....\..\top.eco.cdb
....\..\top.fit.qmsg
....\..\top.hier_info
....\..\top.hif
....\..\top.map.cdb
....\..\top.map.hdb
....\..\top.map.logdb
....\..\top.map.qmsg
....\..\top.pre_map.cdb
....\..\top.pre_map.hdb
....\..\top.psp
....\..\top.rtlv.hdb
....\..\top.rtlv_sg.cdb
....\..\top.rtlv_sg_swap.cdb
....\..\top.sgdiff.cdb
....\..\top.sgdiff.hdb
....\..\top.signalprobe.cdb
....\..\top.sld_design_entry.sci
....\..\top.sld_design_entry_dsc.sci
....\..\top.smp_dump.txt
....\..\top.syn_hier_info
....\..\top.tan.qmsg
....\decoder.bsf
....\settime.bsf
....\settime.vhd
....\state.bsf
....\state.vhd
....\top.asm.rpt
....\top.bdf
....\top.done
....\top.fit.rpt
....\top.fit.summary
....\top.flow.rpt
....\top.map.rpt
....\top.map.summary
....\top.pin
....\top.pof
....\top.qpf
....\top.qsf
....\top.qws
....\top.sof
....\top.tan.rpt
....\top.tan.summary
....\BEEP.bsf
....\beep.vhd
....\counter.bsf
....\counter.vhd
....\db
....\..\top.asm.qmsg
....\..\top.cbx.xml
....\..\top.cmp.cdb
....\..\top.cmp.hdb
....\..\top.cmp.kpt
....\..\top.cmp.logdb
....\..\top.cmp.rdb
....\..\top.cmp.tdb
....\..\top.cmp0.ddb
....\..\top.dbp
....\..\top.db_info
....\..\top.eco.cdb
....\..\top.fit.qmsg
....\..\top.hier_info
....\..\top.hif
....\..\top.map.cdb
....\..\top.map.hdb
....\..\top.map.logdb
....\..\top.map.qmsg
....\..\top.pre_map.cdb
....\..\top.pre_map.hdb
....\..\top.psp
....\..\top.rtlv.hdb
....\..\top.rtlv_sg.cdb
....\..\top.rtlv_sg_swap.cdb
....\..\top.sgdiff.cdb
....\..\top.sgdiff.hdb
....\..\top.signalprobe.cdb
....\..\top.sld_design_entry.sci
....\..\top.sld_design_entry_dsc.sci
....\..\top.smp_dump.txt
....\..\top.syn_hier_info
....\..\top.tan.qmsg
....\decoder.bsf
....\settime.bsf
....\settime.vhd
....\state.bsf
....\state.vhd
....\top.asm.rpt
....\top.bdf
....\top.done
....\top.fit.rpt
....\top.fit.summary
....\top.flow.rpt
....\top.map.rpt
....\top.map.summary
....\top.pin
....\top.pof
....\top.qpf
....\top.qsf
....\top.qws
....\top.sof
....\top.tan.rpt
....\top.tan.summary