文件名称:verilog-encoder
介绍说明－－下载内容均来自于网络，请自行研究使用
JPEG的編碼器
使用VERILOG以硬體實現
也使用MODEL模擬驗證-JPEG encoder using the VERILOG hardware implementation is also used to simulate authentication MODEL
使用VERILOG以硬體實現
也使用MODEL模擬驗證-JPEG encoder using the VERILOG hardware implementation is also used to simulate authentication MODEL
(系统自动生成,下载前可以参看下载内容)
下载文件列表
rtl\add.v
...\barrel_shifter.v
...\cactable.v
...\csa4.v
...\csa5.v
...\csa51.v
...\csa52.v
...\csa6.v
...\dcdiff_htable.v
...\dct.v
...\dctctl.v
...\dct_1d.v
...\dqram64.v
...\FA0.v
...\FA1.v
...\FA2.v
...\FA5.v
...\jpegctl.v
...\JPEGen.v
...\lactable.v
...\packer.v
...\qram64.v
...\scc2.v
...\scc4.v
...\sfifo.v
...\sizetable.v
...\smul.v
...\sub.v
...\transram64.v
...\vlcctl.v
...\zzscan.v
rtl
...\barrel_shifter.v
...\cactable.v
...\csa4.v
...\csa5.v
...\csa51.v
...\csa52.v
...\csa6.v
...\dcdiff_htable.v
...\dct.v
...\dctctl.v
...\dct_1d.v
...\dqram64.v
...\FA0.v
...\FA1.v
...\FA2.v
...\FA5.v
...\jpegctl.v
...\JPEGen.v
...\lactable.v
...\packer.v
...\qram64.v
...\scc2.v
...\scc4.v
...\sfifo.v
...\sizetable.v
...\smul.v
...\sub.v
...\transram64.v
...\vlcctl.v
...\zzscan.v
rtl