文件名称:VERILOGCOMP
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设计一个字节(8 位)比较器。
要求:比较两个字节的大小,如a[7:0]大于 b[7:0]输出高电平,否则输出低电平,改写测试
模型,使其能进行比较全面的测试 。
-design a byte (8) for comparison. Requirements : To compare the size of two bytes, as a greater than [7:0] b [7:0] output margin. Otherwise, low-level output, rewritten test model, in order to enable them to conduct more comprehensive tests.
要求:比较两个字节的大小,如a[7:0]大于 b[7:0]输出高电平,否则输出低电平,改写测试
模型,使其能进行比较全面的测试 。
-design a byte (8) for comparison. Requirements : To compare the size of two bytes, as a greater than [7:0] b [7:0] output margin. Otherwise, low-level output, rewritten test model, in order to enable them to conduct more comprehensive tests.
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