文件名称:SingleLoopSDM_prj
- 所属分类：
- 嵌入式/单片机编程
- 资源属性：
- [Text]
- 上传时间：
- 2012-11-26
- 文件大小：
- 834kb
- 下载次数：
- 0次
- 提 供 者：
- weiji*****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
对频率综合器中的小数分频器进行优化配置，减小参考杂散。-Of the fractional frequency divider in the synthesizer to optimize the configuration, reducing the reference spur.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
SingleLoopSDM_prj\data\testinteger.ds
.................\....\testSDM.ds
.................\....\__simdata010728.ds
.................\....\__simdata032098.ds
.................\....\__simdata113736.ds
.................\de_sim.cfg
.................\de_sim.cfg.old
.................\hpeesofsim.cfg
.................\hpeesofsim.cfg.old
.................\layout.prf
.................\mil_layout.prf
.................\mil_schematic.prf
.................\momServer.log
.................\netlist.log
.................\...works\SigmaDelta3order.ael
.................\........\SigmaDelta3order.atf
.................\........\SigmaDelta3order.bak
.................\........\SigmaDelta3order.dsn
.................\........\SigmaDelta4order.ael
.................\........\SigmaDelta4order.atf
.................\........\SigmaDelta4order.bak
.................\........\SigmaDelta4order.dsn
.................\........\test3order.ael
.................\........\test3order.atf
.................\........\test3order.bak
.................\........\test3order.dsn
.................\........\test4order.ael
.................\........\test4order.dsn
.................\point.txt
.................\point1.txt
.................\project.ads
.................\save_project_state.ael
.................\save_project_state.bak
.................\schematic.prf
.................\test3order.dds
.................\test4order.dds
.................\veriloga\SigmaDelta3order.va
.................\........\SigmaDelta4order.va
.................\data
.................\mom_dsn
.................\networks
.................\synthesis
.................\verification
.................\veriloga
SingleLoopSDM_prj
.................\....\testSDM.ds
.................\....\__simdata010728.ds
.................\....\__simdata032098.ds
.................\....\__simdata113736.ds
.................\de_sim.cfg
.................\de_sim.cfg.old
.................\hpeesofsim.cfg
.................\hpeesofsim.cfg.old
.................\layout.prf
.................\mil_layout.prf
.................\mil_schematic.prf
.................\momServer.log
.................\netlist.log
.................\...works\SigmaDelta3order.ael
.................\........\SigmaDelta3order.atf
.................\........\SigmaDelta3order.bak
.................\........\SigmaDelta3order.dsn
.................\........\SigmaDelta4order.ael
.................\........\SigmaDelta4order.atf
.................\........\SigmaDelta4order.bak
.................\........\SigmaDelta4order.dsn
.................\........\test3order.ael
.................\........\test3order.atf
.................\........\test3order.bak
.................\........\test3order.dsn
.................\........\test4order.ael
.................\........\test4order.dsn
.................\point.txt
.................\point1.txt
.................\project.ads
.................\save_project_state.ael
.................\save_project_state.bak
.................\schematic.prf
.................\test3order.dds
.................\test4order.dds
.................\veriloga\SigmaDelta3order.va
.................\........\SigmaDelta4order.va
.................\data
.................\mom_dsn
.................\networks
.................\synthesis
.................\verification
.................\veriloga
SingleLoopSDM_prj