文件名称:SigCylCPU
介绍说明－－下载内容均来自于网络，请自行研究使用
单周期cpu的设计实现在VHDL中的verilog中实现。
-Design and implementation of single-cycle cpu in VHDL to implement the verilog.
-Design and implementation of single-cycle cpu in VHDL to implement the verilog.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
SigCylCPU\db\mux_3nc.tdf
.........\..\mux_aqc.tdf
.........\..\prev_cmp_SigCyl_CPU.asm.qmsg
.........\..\prev_cmp_SigCyl_CPU.fit.qmsg
.........\..\prev_cmp_SigCyl_CPU.map.qmsg
.........\..\prev_cmp_SigCyl_CPU.qmsg
.........\..\prev_cmp_SigCyl_CPU.sim.qmsg
.........\..\prev_cmp_SigCyl_CPU.tan.qmsg
.........\..\SigCyl_CPU.asm.qmsg
.........\..\SigCyl_CPU.asm_labs.ddb
.........\..\SigCyl_CPU.cbx.xml
.........\..\SigCyl_CPU.cmp.bpm
.........\..\SigCyl_CPU.cmp.cdb
.........\..\SigCyl_CPU.cmp.ecobp
.........\..\SigCyl_CPU.cmp.hdb
.........\..\SigCyl_CPU.cmp.kpt
.........\..\SigCyl_CPU.cmp.logdb
.........\..\SigCyl_CPU.cmp.rdb
.........\..\SigCyl_CPU.cmp.tdb
.........\..\SigCyl_CPU.cmp0.ddb
.........\..\SigCyl_CPU.cmp_merge.kpt
.........\..\SigCyl_CPU.db_info
.........\..\SigCyl_CPU.eco.cdb
.........\..\SigCyl_CPU.eds_overflow
.........\..\SigCyl_CPU.fit.qmsg
.........\..\SigCyl_CPU.fnsim.cdb
.........\..\SigCyl_CPU.fnsim.hdb
.........\..\SigCyl_CPU.fnsim.qmsg
.........\..\SigCyl_CPU.hier_info
.........\..\SigCyl_CPU.hif
.........\..\SigCyl_CPU.lpc.html
.........\..\SigCyl_CPU.lpc.rdb
.........\..\SigCyl_CPU.lpc.txt
.........\..\SigCyl_CPU.map.bpm
.........\..\SigCyl_CPU.map.cdb
.........\..\SigCyl_CPU.map.ecobp
.........\..\SigCyl_CPU.map.hdb
.........\..\SigCyl_CPU.map.kpt
.........\..\SigCyl_CPU.map.logdb
.........\..\SigCyl_CPU.map.qmsg
.........\..\SigCyl_CPU.map_bb.cdb
.........\..\SigCyl_CPU.map_bb.hdb
.........\..\SigCyl_CPU.map_bb.logdb
.........\..\SigCyl_CPU.pre_map.cdb
.........\..\SigCyl_CPU.pre_map.hdb
.........\..\SigCyl_CPU.ram0_Register_b87da43c.hdl.mif
.........\..\SigCyl_CPU.rtlv.hdb
.........\..\SigCyl_CPU.rtlv_sg.cdb
.........\..\SigCyl_CPU.rtlv_sg_swap.cdb
.........\..\SigCyl_CPU.sgdiff.cdb
.........\..\SigCyl_CPU.sgdiff.hdb
.........\..\SigCyl_CPU.sim.cvwf
.........\..\SigCyl_CPU.sim.hdb
.........\..\SigCyl_CPU.sim.qmsg
.........\..\SigCyl_CPU.sim.rdb
.........\..\SigCyl_CPU.simfam
.........\..\SigCyl_CPU.sld_design_entry.sci
.........\..\SigCyl_CPU.sld_design_entry_dsc.sci
.........\..\SigCyl_CPU.syn_hier_info
.........\..\SigCyl_CPU.tan.qmsg
.........\..\SigCyl_CPU.tis_db_list.ddb
.........\..\SigCyl_CPU.tmw_info
.........\..\SigCyl_CPU_global_asgn_op.abo
.........\..\wed.wsf
.........\incremental_db\compiled_partitions\SigCyl_CPU.root_partition.cmp.atm
.........\..............\...................\SigCyl_CPU.root_partition.cmp.dfp
.........\..............\...................\SigCyl_CPU.root_partition.cmp.hdbx
.........\..............\...................\SigCyl_CPU.root_partition.cmp.kpt
.........\..............\...................\SigCyl_CPU.root_partition.cmp.logdb
.........\..............\...................\SigCyl_CPU.root_partition.cmp.rcf
.........\..............\...................\SigCyl_CPU.root_partition.map.atm
.........\..............\...................\SigCyl_CPU.root_partition.map.dpi
.........\..............\...................\SigCyl_CPU.root_partition.map.hdbx
.........\..............\...................\SigCyl_CPU.root_partition.map.kpt
.........\..............\README
.........\SigCyl_CPU.asm.rpt
.........\SigCyl_CPU.done
.........\SigCyl_CPU.fit.rpt
.........\SigCyl_CPU.fit.smsg
.........\SigCyl_CPU.fit.summary
.........\SigCyl_CPU.flow.rpt
.........\SigCyl_CPU.map.rpt
.........\SigCyl_CPU.map.smsg
.........\SigCyl_CPU.map.summary
.........\SigCyl_CPU.pin
.........\SigCyl_CPU.pof
.........\SigCyl_CPU.qpf
.........\SigCyl_CPU.qsf
.........\SigCyl_CPU.qws
.........\SigCyl_CPU.sim.rpt
.........\SigCyl_CPU.sof
.........\SigCyl_CPU.tan.rpt
.........\SigCyl_CPU.tan.summary
.........\SigCyl_CPU.v
.........\SigCyl_CPU.vwf
.........\incremental_db\compiled_partitions
.........\db
.........\incremental_db
SigCylCPU
.........\..\mux_aqc.tdf
.........\..\prev_cmp_SigCyl_CPU.asm.qmsg
.........\..\prev_cmp_SigCyl_CPU.fit.qmsg
.........\..\prev_cmp_SigCyl_CPU.map.qmsg
.........\..\prev_cmp_SigCyl_CPU.qmsg
.........\..\prev_cmp_SigCyl_CPU.sim.qmsg
.........\..\prev_cmp_SigCyl_CPU.tan.qmsg
.........\..\SigCyl_CPU.asm.qmsg
.........\..\SigCyl_CPU.asm_labs.ddb
.........\..\SigCyl_CPU.cbx.xml
.........\..\SigCyl_CPU.cmp.bpm
.........\..\SigCyl_CPU.cmp.cdb
.........\..\SigCyl_CPU.cmp.ecobp
.........\..\SigCyl_CPU.cmp.hdb
.........\..\SigCyl_CPU.cmp.kpt
.........\..\SigCyl_CPU.cmp.logdb
.........\..\SigCyl_CPU.cmp.rdb
.........\..\SigCyl_CPU.cmp.tdb
.........\..\SigCyl_CPU.cmp0.ddb
.........\..\SigCyl_CPU.cmp_merge.kpt
.........\..\SigCyl_CPU.db_info
.........\..\SigCyl_CPU.eco.cdb
.........\..\SigCyl_CPU.eds_overflow
.........\..\SigCyl_CPU.fit.qmsg
.........\..\SigCyl_CPU.fnsim.cdb
.........\..\SigCyl_CPU.fnsim.hdb
.........\..\SigCyl_CPU.fnsim.qmsg
.........\..\SigCyl_CPU.hier_info
.........\..\SigCyl_CPU.hif
.........\..\SigCyl_CPU.lpc.html
.........\..\SigCyl_CPU.lpc.rdb
.........\..\SigCyl_CPU.lpc.txt
.........\..\SigCyl_CPU.map.bpm
.........\..\SigCyl_CPU.map.cdb
.........\..\SigCyl_CPU.map.ecobp
.........\..\SigCyl_CPU.map.hdb
.........\..\SigCyl_CPU.map.kpt
.........\..\SigCyl_CPU.map.logdb
.........\..\SigCyl_CPU.map.qmsg
.........\..\SigCyl_CPU.map_bb.cdb
.........\..\SigCyl_CPU.map_bb.hdb
.........\..\SigCyl_CPU.map_bb.logdb
.........\..\SigCyl_CPU.pre_map.cdb
.........\..\SigCyl_CPU.pre_map.hdb
.........\..\SigCyl_CPU.ram0_Register_b87da43c.hdl.mif
.........\..\SigCyl_CPU.rtlv.hdb
.........\..\SigCyl_CPU.rtlv_sg.cdb
.........\..\SigCyl_CPU.rtlv_sg_swap.cdb
.........\..\SigCyl_CPU.sgdiff.cdb
.........\..\SigCyl_CPU.sgdiff.hdb
.........\..\SigCyl_CPU.sim.cvwf
.........\..\SigCyl_CPU.sim.hdb
.........\..\SigCyl_CPU.sim.qmsg
.........\..\SigCyl_CPU.sim.rdb
.........\..\SigCyl_CPU.simfam
.........\..\SigCyl_CPU.sld_design_entry.sci
.........\..\SigCyl_CPU.sld_design_entry_dsc.sci
.........\..\SigCyl_CPU.syn_hier_info
.........\..\SigCyl_CPU.tan.qmsg
.........\..\SigCyl_CPU.tis_db_list.ddb
.........\..\SigCyl_CPU.tmw_info
.........\..\SigCyl_CPU_global_asgn_op.abo
.........\..\wed.wsf
.........\incremental_db\compiled_partitions\SigCyl_CPU.root_partition.cmp.atm
.........\..............\...................\SigCyl_CPU.root_partition.cmp.dfp
.........\..............\...................\SigCyl_CPU.root_partition.cmp.hdbx
.........\..............\...................\SigCyl_CPU.root_partition.cmp.kpt
.........\..............\...................\SigCyl_CPU.root_partition.cmp.logdb
.........\..............\...................\SigCyl_CPU.root_partition.cmp.rcf
.........\..............\...................\SigCyl_CPU.root_partition.map.atm
.........\..............\...................\SigCyl_CPU.root_partition.map.dpi
.........\..............\...................\SigCyl_CPU.root_partition.map.hdbx
.........\..............\...................\SigCyl_CPU.root_partition.map.kpt
.........\..............\README
.........\SigCyl_CPU.asm.rpt
.........\SigCyl_CPU.done
.........\SigCyl_CPU.fit.rpt
.........\SigCyl_CPU.fit.smsg
.........\SigCyl_CPU.fit.summary
.........\SigCyl_CPU.flow.rpt
.........\SigCyl_CPU.map.rpt
.........\SigCyl_CPU.map.smsg
.........\SigCyl_CPU.map.summary
.........\SigCyl_CPU.pin
.........\SigCyl_CPU.pof
.........\SigCyl_CPU.qpf
.........\SigCyl_CPU.qsf
.........\SigCyl_CPU.qws
.........\SigCyl_CPU.sim.rpt
.........\SigCyl_CPU.sof
.........\SigCyl_CPU.tan.rpt
.........\SigCyl_CPU.tan.summary
.........\SigCyl_CPU.v
.........\SigCyl_CPU.vwf
.........\incremental_db\compiled_partitions
.........\db
.........\incremental_db
SigCylCPU