文件名称:i2cjiekouchengxu
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这是一个IIC的接口程序，是夏宇闻编的书《verilog 数字系统设计教程》的IIC的源码，很通俗易懂-IIC interface procedures, Xia Wen is the book series "verilog Digital System Design Guide," the IIC the source, very user-friendly
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压缩包 : 63535319i2cjiekouchengxu.rar 列表 i2c\bench\CVS\Entries i2c\bench\CVS\Repository i2c\bench\CVS\Root i2c\bench\CVS i2c\bench\verilog\CVS\Entries i2c\bench\verilog\CVS\Repository i2c\bench\verilog\CVS\Root i2c\bench\verilog\CVS i2c\bench\verilog\i2c_slave_model.v i2c\bench\verilog\i2c_slave_model.v.bak i2c\bench\verilog\spi_slave_model.v i2c\bench\verilog\spi_slave_model.v.bak i2c\bench\verilog\tst_bench_top.v i2c\bench\verilog\tst_bench_top.v.bak i2c\bench\verilog\wb_master_model.v i2c\bench\verilog\wb_master_model.v.bak i2c\bench\verilog i2c\bench i2c\CVS\Entries i2c\CVS\Repository i2c\CVS\Root i2c\CVS i2c\doc\CVS\Entries i2c\doc\CVS\Repository i2c\doc\CVS\Root i2c\doc\CVS i2c\doc\i2c_specs.pdf i2c\doc\src\CVS\Entries i2c\doc\src\CVS\Repository i2c\doc\src\CVS\Root i2c\doc\src\CVS i2c\doc\src\I2C_specs.doc i2c\doc\src i2c\doc i2c\rtl\CVS\Entries i2c\rtl\CVS\Repository i2c\rtl\CVS\Root i2c\rtl\CVS i2c\rtl\verilog\CVS\Entries i2c\rtl\verilog\CVS\Repository i2c\rtl\verilog\CVS\Root i2c\rtl\verilog\CVS i2c\rtl\verilog\i2c_master_bit_ctrl.v i2c\rtl\verilog\i2c_master_bit_ctrl.v.bak i2c\rtl\verilog\i2c_master_byte_ctrl.v i2c\rtl\verilog\i2c_master_byte_ctrl.v.bak i2c\rtl\verilog\i2c_master_defines.v i2c\rtl\verilog\i2c_master_top.v i2c\rtl\verilog\i2c_master_top.v.bak i2c\rtl\verilog\timescale.v i2c\rtl\verilog i2c\rtl\vhdl\CVS\Entries i2c\rtl\vhdl\CVS\Repository i2c\rtl\vhdl\CVS\Root i2c\rtl\vhdl\CVS i2c\rtl\vhdl\I2C.VHD i2c\rtl\vhdl\i2c_master_bit_ctrl.vhd i2c\rtl\vhdl\i2c_master_byte_ctrl.vhd i2c\rtl\vhdl\i2c_master_top.vhd i2c\rtl\vhdl\readme i2c\rtl\vhdl\tst_ds1621.vhd i2c\rtl\vhdl i2c\rtl i2c\sim\CVS\Entries i2c\sim\CVS\Repository i2c\sim\CVS\Root i2c\sim\CVS i2c\sim\i2c.cr.mti i2c\sim\i2c.mpf i2c\sim\i2c_verilog\CVS\Entries i2c\sim\i2c_verilog\CVS\Repository i2c\sim\i2c_verilog\CVS\Root i2c\sim\i2c_verilog\CVS i2c\sim\i2c_verilog\run\bench.vcd i2c\sim\i2c_verilog\run\CVS\Entries i2c\sim\i2c_verilog\run\CVS\Repository i2c\sim\i2c_verilog\run\CVS\Root i2c\sim\i2c_verilog\run\CVS i2c\sim\i2c_verilog\run\INCA_libs\CVS\Entries i2c\sim\i2c_verilog\run\INCA_libs\CVS\Repository i2c\sim\i2c_verilog\run\INCA_libs\CVS\Root i2c\sim\i2c_verilog\run\INCA_libs\CVS i2c\sim\i2c_verilog\run\INCA_libs i2c\sim\i2c_verilog\run\ncverilog.key i2c\sim\i2c_verilog\run\ncverilog.log i2c\sim\i2c_verilog\run\run i2c\sim\i2c_verilog\run\waves\CVS\Entries i2c\sim\i2c_verilog\run\waves\CVS\Repository i2c\sim\i2c_verilog\run\waves\CVS\Root i2c\sim\i2c_verilog\run\waves\CVS i2c\sim\i2c_verilog\run\waves i2c\sim\i2c_verilog\run i2c\sim\i2c_verilog i2c\sim\vsim.wlf i2c\sim\work\@m@a@x@i@i_@p@r@i@m_@d@f@f@e\verilog.asm i2c\sim\work\@m@a@x@i@i_@p@r@i@m_@d@f@f@e\_primary.dat i2c\sim\work\@m@a@x@i@i_@p@r@i@m_@d@f@f@e\_primary.vhd i2c\sim\work\@m@a@x@i@i_@p@r@i@m_@d@f@f@e i2c\sim\work\delay\verilog.asm i2c\sim\work\delay\_primary.dat i2c\sim\work\delay\_primary.vhd i2c\sim\work\delay i2c\sim\work\i2c_master_bit_ctrl\verilog.asm i2c\sim\work\i2c_master_bit_ctrl\_primary.dat i2c\sim\work\i2c_master_bit_ctrl\_primary.vhd i2c\sim\work\i2c_master_bit_ctrl i2c\sim\work\i2c_master_byte_ctrl\verilog.asm i2c\sim\work\i2c_master_byte_ctrl\_primary.dat i2c\sim\work\i2c_master_byte_ctrl\_primary.vhd i2c\sim\work\i2c_master_byte_ctrl i2c\sim\work\i2c_master_top\verilog.asm i2c\sim\work\i2c_master_top\_primary.dat i2c\sim\work\i2c_master_top\_primary.vhd i2c\sim\work\i2c_master_top i2c\sim\work\i2c_slave_model\verilog.asm i2c\sim\work\i2c_slave_model\_primary.dat i2c\sim\work\i2c_slave_model\_primary.vhd i2c\sim\work\i2c_slave_model i2c\sim\work\maxii_and1\verilog.asm i2c\sim\work\maxii_and1\_primary.dat i2c\sim\work\maxii_and1\_primary.vhd i2c\sim\work\maxii_and1 i2c\sim\work\maxii_and16\verilog.asm i2c\sim\work\maxii_and16\_primary.dat i2c\sim\work\maxii_and16\_primary.vhd i2c\sim\work\maxii_and16 i2c\sim\work\maxii_asynch_lcell\verilog.asm i2c\sim\work\maxii_asynch_lcell\_primary.dat i2c\sim\work\maxii_asynch_lcell\_primary.vhd i2c\sim\work\maxii_asynch_lcell i2c\sim\work\maxii_b17mux21\verilog.asm i2c\sim\work\maxii_b17mux21\_primary.dat i2c\sim\work\maxii_b17mux21\_primary.vhd i2c\sim\work\maxii_b17mux21 i2c\sim\work\maxii_b5mux21\verilog.asm i2c\sim\work\maxii_b5mux21\_primary.dat i2c\sim\work\maxii_b5mux21\_primary.vhd i2c\sim\work\maxii_b5mux21 i2c\sim\work\maxii_bmux21\verilog.asm i2c\sim\work\maxii_bmux21\_primary.dat i2c\sim\work\maxii_bmux21\_primary.vhd i2c\sim\work\maxii_bmux21 i2c\sim\work\maxii_dffe\verilog.asm i2c\sim\work\maxii_dffe\_primary.dat i2c\sim\work\maxii_dffe\_primary.vhd i2c\sim\work\maxii_dffe i2c\sim\work\maxii_io\verilog.asm i2c\sim\work\maxii_io\_primary.dat i2c\sim\work\maxii_io\_primary.vhd i2c\sim\work\maxii_io i2c\sim\work\maxii_latch\verilog.asm i2c\sim\work\maxii_latch\_primary.dat i2c\sim\work\maxii_latch\_primary.vhd i2c\sim\work\maxii_latch i2c\sim\work\maxii_lcell\verilog.asm i2c\sim\work\maxii_lcell\_primary.dat i2c\sim\work\maxii_lcell\_primary.vhd i2c\sim\work\maxii_lcell i2c\sim\work\maxii_lcell_register\verilog.asm i2c\sim\work\maxii_lcell_register\_primary.dat i2c\sim\work\maxii_lcell_register\_primary.vhd i2c\sim\work\maxii_lcell_register i2c\sim\work\maxii_mux21\verilog.asm i2c\sim\work\maxii_mux21\_primary.dat i2c\sim\work\maxii_mux21\_primary.vhd i2c\sim\work\maxii_mux21 i2c\sim\work\maxii_mux41\verilog.asm i2c\sim\work\maxii_mux41\_primary.dat i2c\sim\work\maxii_mux41\_primary.vhd i2c\sim\work\maxii_mux41 i2c\sim\work\maxii_nmux21\verilog.asm i2c\sim\work\maxii_nmux21\_primary.dat i2c\sim\work\maxii_nmux21\_primary.vhd i2c\sim\work\maxii_nmux21 i2c\sim\work\maxii_routing_wire\verilog.asm i2c\sim\work\maxii_routing_wire\_primary.dat i2c\sim\work\maxii_routing_wire\_primary.vhd i2c\sim\work\maxii_routing_wire i2c\sim\work\maxii_ufm\verilog.asm i2c\sim\work\maxii_ufm\_primary.dat i2c\sim\work\maxii_ufm\_primary.vhd i2c\sim\work\maxii_ufm i2c\sim\work\tst_bench_top\verilog.asm i2c\sim\work\tst_bench_top\_primary.dat i2c\sim\work\tst_bench_top\_primary.vhd i2c\sim\work\tst_bench_top i2c\sim\work\wb_master_model\verilog.asm i2c\sim\work\wb_master_model\_primary.dat i2c\sim\work\wb_master_model\_primary.vhd i2c\sim\work\wb_master_model i2c\sim\work\_info i2c\sim\work i2c\sim i2c\software\CVS\Entries i2c\software\CVS\Repository i2c\software\CVS\Root i2c\software\CVS i2c\software\drivers\CVS\Entries i2c\software\drivers\CVS\Repository i2c\software\drivers\CVS\Root i2c\software\drivers\CVS i2c\software\drivers i2c\software\include\CVS\Entries i2c\software\include\CVS\Repository i2c\software\include\CVS\Root i2c\software\include\CVS i2c\software\include\oc_i2c_master.h i2c\software\include i2c\software i2c\verilog\CVS\Entries i2c\verilog\CVS\Repository i2c\verilog\CVS\Root i2c\verilog\CVS i2c\verilog i2c\vhdl\CVS\Entries i2c\vhdl\CVS\Repository i2c\vhdl\CVS\Root i2c\vhdl\CVS i2c\vhdl i2c