文件名称:huaqiaodaxue--DE2_NET
介绍说明－－下载内容均来自于网络，请自行研究使用
华侨大学专用实验程序代码，实现de2网络发送数据包，华侨大学实验室。
华侨大学eda实验室专用-Chinese University of dedicated experimental program code, data packets sent over the network to achieve de2, Huaqiao University laboratory. Huaqiao University eda laboratory dedicated
华侨大学eda实验室专用-Chinese University of dedicated experimental program code, data packets sent over the network to achieve de2, Huaqiao University laboratory. Huaqiao University eda laboratory dedicated
(系统自动生成,下载前可以参看下载内容)
下载文件列表
DE2_NET\.metadata\.lock
.......\.........\.plugins\org.eclipse.core.resources\.projects\hello_led_0\.properties
.......\.........\........\..........................\.........\..........._syslib\.properties
.......\.........\........\..........................\.root\9.tree
.......\.........\........\..........................\.safetable\org.eclipse.core.resources
.......\.........\........\..................untime\.settings\org.eclipse.cdt.core.prefs
.......\.........\........\........................\.........\org.eclipse.cdt.debug.core.prefs
.......\.........\........\........................\.........\org.eclipse.cdt.ui.prefs
.......\.........\........\........................\.........\org.eclipse.team.cvs.ui.prefs
.......\.........\........\........................\.........\org.eclipse.team.ui.prefs
.......\.........\........\........................\.........\org.eclipse.ui.prefs
.......\.........\........\........................\.........\org.eclipse.ui.workbench.prefs
.......\.........\........\............ui.workbench\dialog_settings.xml
.......\.........\........\........................\workbench.xml
.......\.........\version.ini
.......\.sopc_builder\install.ptf
.......\altpllpll_0.ppf
.......\Audio_0.v
.......\......DAC_FIFO\cb_generator.pl
.......\..............\class.ptf
.......\..............\hdl\AUDIO_DAC_FIFO.v
.......\..............\...\FIFO_16_256.v
.......\AUDIO_DAC_FIFO.v
.......\Audio_PLL.ppf
.......\Audio_PLL.v
.......\bht_ram.mif
.......\Binary_VGA_Controller\cb_generator.pl
.......\.....................\class.ptf
.......\.....................\hdl\Img_DATA.hex
.......\.....................\...\Img_RAM.v
.......\.....................\...\VGA_Controller.v
.......\.....................\...\VGA_NIOS_CTRL.v
.......\.....................\...\VGA_OSD_RAM.v
.......\.....................\...\VGA_Param.h
.......\.....................\inc\VGA.c
.......\.....................\...\VGA.h
.......\button_pio.v
.......\clock_0.v
.......\clock_1.v
.......\cpu_0.ocp
.......\cpu_0.v
.......\cpu_0.vo
.......\cpu_0_bht_ram.mif
.......\cpu_0_dc_tag_ram.mif
.......\cpu_0_ic_tag_ram.mif
.......\cpu_0_jtag_debug_module.v
.......\cpu_0_jtag_debug_module_wrapper.v
.......\cpu_0_mult_cell.v
.......\cpu_0_ociram_default_contents.mif
.......\cpu_0_rf_ram_a.mif
.......\cpu_0_rf_ram_b.mif
.......\cpu_0_test_bench.v
.......\db\DE2_NET.db_info
.......\..\DE2_NET.eco.cdb
.......\..\DE2_NET.sld_design_entry.sci
.......\dc_tag_ram.mif
.......\DE2_Board\class.ptf
.......\.........\system\.sopc_builder\install.ptf
.......\.........\......\asmi.v
.......\.........\......\cmp_state.ini
.......\.........\......\cpu_0.ocp
.......\.........\......\cpu_0.v
.......\.........\......\cpu_0_test_bench.v
.......\.........\......\data_RAM.hex
.......\.........\......\data_RAM.v
.......\.........\......\DE2_Board.asm.rpt
.......\.........\......\DE2_Board.bsf
.......\.........\......\DE2_Board.cdf
.......\.........\......\DE2_Board.done
.......\.........\......\DE2_Board.fit.eqn
.......\.........\......\DE2_Board.fit.rpt
.......\.........\......\DE2_Board.fit.summary
.......\.........\......\DE2_Board.flow.rpt
.......\.........\......\DE2_Board.map.eqn
.......\.........\......\DE2_Board.map.rpt
.......\.........\......\DE2_Board.map.summary
.......\.........\......\DE2_Board.pin
.......\.........\......\DE2_Board.pof
.......\.........\......\DE2_Board.ptf
.......\.........\......\DE2_Board.ptf.5.00
.......\.........\......\DE2_Board.qpf
.......\.........\......\DE2_Board.qsf
.......\.........\......\DE2_Board.qws
.......\.........\......\DE2_Board.sof
.......\.........\......\DE2_Board.tan.rpt
.......\.........\......\DE2_Board.tan.summary
.......\.........\......\DE2_Board.v
.......\.........\......\DE2_Board_assignment_defaults.qdf
.......\.........\......\DE2_Board_generation_script
.......\.........\......\DE2_Board_log.txt
.......\.........\......\DE2_Board_setup_quartus.tcl
.......\.........\......\...........im\atail-f.pl
.......\.........\......\.............\contents_file_warning.txt
.......\.........\......\.............\jtag_uart_0_inpu
.......\.........\.plugins\org.eclipse.core.resources\.projects\hello_led_0\.properties
.......\.........\........\..........................\.........\..........._syslib\.properties
.......\.........\........\..........................\.root\9.tree
.......\.........\........\..........................\.safetable\org.eclipse.core.resources
.......\.........\........\..................untime\.settings\org.eclipse.cdt.core.prefs
.......\.........\........\........................\.........\org.eclipse.cdt.debug.core.prefs
.......\.........\........\........................\.........\org.eclipse.cdt.ui.prefs
.......\.........\........\........................\.........\org.eclipse.team.cvs.ui.prefs
.......\.........\........\........................\.........\org.eclipse.team.ui.prefs
.......\.........\........\........................\.........\org.eclipse.ui.prefs
.......\.........\........\........................\.........\org.eclipse.ui.workbench.prefs
.......\.........\........\............ui.workbench\dialog_settings.xml
.......\.........\........\........................\workbench.xml
.......\.........\version.ini
.......\.sopc_builder\install.ptf
.......\altpllpll_0.ppf
.......\Audio_0.v
.......\......DAC_FIFO\cb_generator.pl
.......\..............\class.ptf
.......\..............\hdl\AUDIO_DAC_FIFO.v
.......\..............\...\FIFO_16_256.v
.......\AUDIO_DAC_FIFO.v
.......\Audio_PLL.ppf
.......\Audio_PLL.v
.......\bht_ram.mif
.......\Binary_VGA_Controller\cb_generator.pl
.......\.....................\class.ptf
.......\.....................\hdl\Img_DATA.hex
.......\.....................\...\Img_RAM.v
.......\.....................\...\VGA_Controller.v
.......\.....................\...\VGA_NIOS_CTRL.v
.......\.....................\...\VGA_OSD_RAM.v
.......\.....................\...\VGA_Param.h
.......\.....................\inc\VGA.c
.......\.....................\...\VGA.h
.......\button_pio.v
.......\clock_0.v
.......\clock_1.v
.......\cpu_0.ocp
.......\cpu_0.v
.......\cpu_0.vo
.......\cpu_0_bht_ram.mif
.......\cpu_0_dc_tag_ram.mif
.......\cpu_0_ic_tag_ram.mif
.......\cpu_0_jtag_debug_module.v
.......\cpu_0_jtag_debug_module_wrapper.v
.......\cpu_0_mult_cell.v
.......\cpu_0_ociram_default_contents.mif
.......\cpu_0_rf_ram_a.mif
.......\cpu_0_rf_ram_b.mif
.......\cpu_0_test_bench.v
.......\db\DE2_NET.db_info
.......\..\DE2_NET.eco.cdb
.......\..\DE2_NET.sld_design_entry.sci
.......\dc_tag_ram.mif
.......\DE2_Board\class.ptf
.......\.........\system\.sopc_builder\install.ptf
.......\.........\......\asmi.v
.......\.........\......\cmp_state.ini
.......\.........\......\cpu_0.ocp
.......\.........\......\cpu_0.v
.......\.........\......\cpu_0_test_bench.v
.......\.........\......\data_RAM.hex
.......\.........\......\data_RAM.v
.......\.........\......\DE2_Board.asm.rpt
.......\.........\......\DE2_Board.bsf
.......\.........\......\DE2_Board.cdf
.......\.........\......\DE2_Board.done
.......\.........\......\DE2_Board.fit.eqn
.......\.........\......\DE2_Board.fit.rpt
.......\.........\......\DE2_Board.fit.summary
.......\.........\......\DE2_Board.flow.rpt
.......\.........\......\DE2_Board.map.eqn
.......\.........\......\DE2_Board.map.rpt
.......\.........\......\DE2_Board.map.summary
.......\.........\......\DE2_Board.pin
.......\.........\......\DE2_Board.pof
.......\.........\......\DE2_Board.ptf
.......\.........\......\DE2_Board.ptf.5.00
.......\.........\......\DE2_Board.qpf
.......\.........\......\DE2_Board.qsf
.......\.........\......\DE2_Board.qws
.......\.........\......\DE2_Board.sof
.......\.........\......\DE2_Board.tan.rpt
.......\.........\......\DE2_Board.tan.summary
.......\.........\......\DE2_Board.v
.......\.........\......\DE2_Board_assignment_defaults.qdf
.......\.........\......\DE2_Board_generation_script
.......\.........\......\DE2_Board_log.txt
.......\.........\......\DE2_Board_setup_quartus.tcl
.......\.........\......\...........im\atail-f.pl
.......\.........\......\.............\contents_file_warning.txt
.......\.........\......\.............\jtag_uart_0_inpu