文件名称:lab2
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D-type storage elements
The circuit below contains three different types of storage element: a gated (transparent) D latch, a positive-edge triggered and negative edge triggered D-type flip-flops.
Write a VHDL file that instantiates the three storage elements. You can use the code for the gated D-type below as an example to get started. Use a similar coding style for the other flip-flops.
Compile your code and use the Technology Viewer to examine the implemented circuit and to determine how the synthesis process has allocated your circuit to the internal resources in the FPGA.
Using the waveform below as a guide, create a Vector Waveform File (.vwf) that specifies the inputs and expected outputs of the circuit. Perform a functional simulation to obtain the three output signals. Observe the different behaviour of the three storage elements.-D-type storage elements
The circuit below contains three different types of storage element: a gated (transparent) D latch, a positive-edge triggered and negative edge triggered D-type flip-flops.
Write a VHDL file that instantiates the three storage elements. You can use the code for the gated D-type below as an example to get started. Use a similar coding style for the other flip-flops.
Compile your code and use the Technology Viewer to examine the implemented circuit and to determine how the synthesis process has allocated your circuit to the internal resources in the FPGA.
Using the waveform below as a guide, create a Vector Waveform File (.vwf) that specifies the inputs and expected outputs of the circuit. Perform a functional simulation to obtain the three output signals. Observe the different behaviour of the three storage elements.
The circuit below contains three different types of storage element: a gated (transparent) D latch, a positive-edge triggered and negative edge triggered D-type flip-flops.
Write a VHDL file that instantiates the three storage elements. You can use the code for the gated D-type below as an example to get started. Use a similar coding style for the other flip-flops.
Compile your code and use the Technology Viewer to examine the implemented circuit and to determine how the synthesis process has allocated your circuit to the internal resources in the FPGA.
Using the waveform below as a guide, create a Vector Waveform File (.vwf) that specifies the inputs and expected outputs of the circuit. Perform a functional simulation to obtain the three output signals. Observe the different behaviour of the three storage elements.-D-type storage elements
The circuit below contains three different types of storage element: a gated (transparent) D latch, a positive-edge triggered and negative edge triggered D-type flip-flops.
Write a VHDL file that instantiates the three storage elements. You can use the code for the gated D-type below as an example to get started. Use a similar coding style for the other flip-flops.
Compile your code and use the Technology Viewer to examine the implemented circuit and to determine how the synthesis process has allocated your circuit to the internal resources in the FPGA.
Using the waveform below as a guide, create a Vector Waveform File (.vwf) that specifies the inputs and expected outputs of the circuit. Perform a functional simulation to obtain the three output signals. Observe the different behaviour of the three storage elements.
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下载文件列表
lab2\d_latch.qpf
....\d_latch.qsf
....\counter.vhd
....\d_latch.map.summary
....\counter.flow.rpt
....\counter.asm.rpt
....\counter.tan.summary
....\counter.tan.rpt
....\counter.done
....\counter.vhd.bak
....\counter.map.rpt
....\counter.qws
....\d_type.vwf
....\d_type.sim.rpt
....\d_type.qws
....\B_counter.qpf
....\B_counter.qsf
....\B_counter.vhd
....\B_counter.map.summary
....\B_counter.map.rpt
....\B_counter.flow.rpt
....\B_counter.vhd.bak
....\B_counter.pin
....\B_counter.fit.smsg
....\B_counter.fit.summary
....\B_counter.fit.rpt
....\B_counter.sof
....\B_counter.pof
....\B_counter.asm.rpt
....\B_counter.dpf
....\d_latch.pin
....\d_latch.fit.smsg
....\d_latch.fit.summary
....\B_counter.tan.summary
....\B_counter.tan.rpt
....\d_latch.sof
....\d_latch.pof
....\B_counter.done
....\B_counter.qws
....\d_latch.tan.summary
....\d_latch.done
....\positive.qpf
....\positive.qsf
....\positive.map.summary
....\positive.vhd.bak
....\positive.vhd
....\positive.map.rpt
....\positive.pin
....\positive.fit.smsg
....\positive.fit.summary
....\positive.fit.rpt
....\positive.sof
....\positive.pof
....\positive.asm.rpt
....\positive.tan.summary
....\positive.tan.rpt
....\positive.flow.rpt
....\positive.done
....\negetive.qpf
....\negetive.qsf
....\negetive.map.summary
....\negetive.pin
....\negetive.fit.smsg
....\negetive.fit.summary
....\negetive.sof
....\negetive.pof
....\negetive.tan.summary
....\negetive.done
....\d_latch.map.rpt
....\d_latch.fit.rpt
....\d_latch.asm.rpt
....\d_latch.tan.rpt
....\d_latch.flow.rpt
....\d_latch.qws
....\positive.qws
....\negetive.vhd.bak
....\negetive.vhd
....\negetive.map.rpt
....\negetive.fit.rpt
....\negetive.asm.rpt
....\negetive.tan.rpt
....\negetive.flow.rpt
....\negetive.qws
....\d_type.qpf
....\d_type.qsf
....\d_latch.vhd.bak
....\d_latch.vhd
....\counter.qpf
....\counter.qsf
....\d_type.map.summary
....\d_type.vhd.bak
....\d_type.vhd
....\d_type.map.rpt
....\d_type.pin
....\d_type.fit.smsg
....\d_type.fit.summary
....\d_type.fit.rpt
....\d_type.sof
....\d_type.pof
....\d_type.asm.rpt
....\d_latch.qsf
....\counter.vhd
....\d_latch.map.summary
....\counter.flow.rpt
....\counter.asm.rpt
....\counter.tan.summary
....\counter.tan.rpt
....\counter.done
....\counter.vhd.bak
....\counter.map.rpt
....\counter.qws
....\d_type.vwf
....\d_type.sim.rpt
....\d_type.qws
....\B_counter.qpf
....\B_counter.qsf
....\B_counter.vhd
....\B_counter.map.summary
....\B_counter.map.rpt
....\B_counter.flow.rpt
....\B_counter.vhd.bak
....\B_counter.pin
....\B_counter.fit.smsg
....\B_counter.fit.summary
....\B_counter.fit.rpt
....\B_counter.sof
....\B_counter.pof
....\B_counter.asm.rpt
....\B_counter.dpf
....\d_latch.pin
....\d_latch.fit.smsg
....\d_latch.fit.summary
....\B_counter.tan.summary
....\B_counter.tan.rpt
....\d_latch.sof
....\d_latch.pof
....\B_counter.done
....\B_counter.qws
....\d_latch.tan.summary
....\d_latch.done
....\positive.qpf
....\positive.qsf
....\positive.map.summary
....\positive.vhd.bak
....\positive.vhd
....\positive.map.rpt
....\positive.pin
....\positive.fit.smsg
....\positive.fit.summary
....\positive.fit.rpt
....\positive.sof
....\positive.pof
....\positive.asm.rpt
....\positive.tan.summary
....\positive.tan.rpt
....\positive.flow.rpt
....\positive.done
....\negetive.qpf
....\negetive.qsf
....\negetive.map.summary
....\negetive.pin
....\negetive.fit.smsg
....\negetive.fit.summary
....\negetive.sof
....\negetive.pof
....\negetive.tan.summary
....\negetive.done
....\d_latch.map.rpt
....\d_latch.fit.rpt
....\d_latch.asm.rpt
....\d_latch.tan.rpt
....\d_latch.flow.rpt
....\d_latch.qws
....\positive.qws
....\negetive.vhd.bak
....\negetive.vhd
....\negetive.map.rpt
....\negetive.fit.rpt
....\negetive.asm.rpt
....\negetive.tan.rpt
....\negetive.flow.rpt
....\negetive.qws
....\d_type.qpf
....\d_type.qsf
....\d_latch.vhd.bak
....\d_latch.vhd
....\counter.qpf
....\counter.qsf
....\d_type.map.summary
....\d_type.vhd.bak
....\d_type.vhd
....\d_type.map.rpt
....\d_type.pin
....\d_type.fit.smsg
....\d_type.fit.summary
....\d_type.fit.rpt
....\d_type.sof
....\d_type.pof
....\d_type.asm.rpt