文件名称:can_controller
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基于FPGA的VHDL，can总线控制的设计与实现，在ISE下弄的。-FPGA-based VHDL, can control the design and implementation of the bus, get under the ISE' s.
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下载文件列表
can_controller\can_acf.v
..............\can_bsp.v
..............\can_btl.v
..............\can_controller.cr.mti
..............\can_controller.mpf
..............\can_crc.v
..............\can_defines.v
..............\can_fifo.v
..............\can_ibo.v
..............\can_register.v
..............\can_registers.v
..............\can_register_asyn.v
..............\can_register_asyn_syn.v
..............\can_register_syn.v
..............\can_testbench.v
..............\can_testbench_defines.v
..............\can_top.v
..............\timescale.v
..............\transcript
..............\vsim.wlf
..............\work\_info
..............\....\can_top\verilog.asm
..............\....\.......\_primary.dat
..............\....\.......\_primary.vhd
..............\....\.....estbench\verilog.asm
..............\....\.............\_primary.dat
..............\....\.............\_primary.vhd
..............\....\....register_syn\verilog.asm
..............\....\................\_primary.dat
..............\....\................\_primary.vhd
..............\....\.............asyn_syn\verilog.asm
..............\....\.....................\_primary.dat
..............\....\.....................\_primary.vhd
..............\....\.................\verilog.asm
..............\....\.................\_primary.dat
..............\....\.................\_primary.vhd
..............\....\............s\verilog.asm
..............\....\.............\_primary.dat
..............\....\.............\_primary.vhd
..............\....\............\verilog.asm
..............\....\............\_primary.dat
..............\....\............\_primary.vhd
..............\....\....ibo\verilog.asm
..............\....\.......\_primary.dat
..............\....\.......\_primary.vhd
..............\....\....fifo\verilog.asm
..............\....\........\_primary.dat
..............\....\can_top
..............\....\can_testbench
..............\....\can_register_syn
..............\....\can_register_asyn_syn
..............\....\can_register_asyn
..............\....\can_registers
..............\....\can_register
..............\....\can_ibo
..............\....\can_fifo
..............\work
can_controller
..............\can_bsp.v
..............\can_btl.v
..............\can_controller.cr.mti
..............\can_controller.mpf
..............\can_crc.v
..............\can_defines.v
..............\can_fifo.v
..............\can_ibo.v
..............\can_register.v
..............\can_registers.v
..............\can_register_asyn.v
..............\can_register_asyn_syn.v
..............\can_register_syn.v
..............\can_testbench.v
..............\can_testbench_defines.v
..............\can_top.v
..............\timescale.v
..............\transcript
..............\vsim.wlf
..............\work\_info
..............\....\can_top\verilog.asm
..............\....\.......\_primary.dat
..............\....\.......\_primary.vhd
..............\....\.....estbench\verilog.asm
..............\....\.............\_primary.dat
..............\....\.............\_primary.vhd
..............\....\....register_syn\verilog.asm
..............\....\................\_primary.dat
..............\....\................\_primary.vhd
..............\....\.............asyn_syn\verilog.asm
..............\....\.....................\_primary.dat
..............\....\.....................\_primary.vhd
..............\....\.................\verilog.asm
..............\....\.................\_primary.dat
..............\....\.................\_primary.vhd
..............\....\............s\verilog.asm
..............\....\.............\_primary.dat
..............\....\.............\_primary.vhd
..............\....\............\verilog.asm
..............\....\............\_primary.dat
..............\....\............\_primary.vhd
..............\....\....ibo\verilog.asm
..............\....\.......\_primary.dat
..............\....\.......\_primary.vhd
..............\....\....fifo\verilog.asm
..............\....\........\_primary.dat
..............\....\can_top
..............\....\can_testbench
..............\....\can_register_syn
..............\....\can_register_asyn_syn
..............\....\can_register_asyn
..............\....\can_registers
..............\....\can_register
..............\....\can_ibo
..............\....\can_fifo
..............\work
can_controller