文件名称:MIPS_CPU-verilog
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用Verilog语言写的一个MIPS微处理器，包含常见指令的21条数据通路。-Verilog language used to write a MIPS microprocessor, including the 21 common data path instruction
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下载文件列表
MIPS_CPU-verilog\Adder32.v
................\Adder32.v.bak
................\ALU.v
................\ALU.v.bak
................\ALUController.v
................\ALUController.v.bak
................\Controller.v
................\Controller.v.bak
................\CPU.v
................\CPU.v.bak
................\DataMem.v
................\DataMem.v.bak
................\dff.cr.mti
................\dff.mpf
................\InsMem.v
................\InsMem.v.bak
................\MIPSCPU.cr.mti
................\MIPSCPU.mpf
................\Mux2to1.v.bak
................\Mux2to1_32.v
................\Mux2to1_32.v.bak
................\Mux2to1_5.v
................\Mux2to1_5.v.bak
................\PC.v
................\PC.v.bak
................\RegisterDump.v
................\RegisterDump.v.bak
................\ShiftLeft2.v.bak
................\ShiftLeft2_16.v.bak
................\ShiftLeft2_26.v
................\ShiftLeft2_26.v.bak
................\ShiftLeft2_32.v
................\ShiftLeft2_32.v.bak
................\SignExt.v
................\SignExt.v.bak
................\transcript
................\vsim.wlf
MIPS_CPU-verilog
................\Adder32.v.bak
................\ALU.v
................\ALU.v.bak
................\ALUController.v
................\ALUController.v.bak
................\Controller.v
................\Controller.v.bak
................\CPU.v
................\CPU.v.bak
................\DataMem.v
................\DataMem.v.bak
................\dff.cr.mti
................\dff.mpf
................\InsMem.v
................\InsMem.v.bak
................\MIPSCPU.cr.mti
................\MIPSCPU.mpf
................\Mux2to1.v.bak
................\Mux2to1_32.v
................\Mux2to1_32.v.bak
................\Mux2to1_5.v
................\Mux2to1_5.v.bak
................\PC.v
................\PC.v.bak
................\RegisterDump.v
................\RegisterDump.v.bak
................\ShiftLeft2.v.bak
................\ShiftLeft2_16.v.bak
................\ShiftLeft2_26.v
................\ShiftLeft2_26.v.bak
................\ShiftLeft2_32.v
................\ShiftLeft2_32.v.bak
................\SignExt.v
................\SignExt.v.bak
................\transcript
................\vsim.wlf
MIPS_CPU-verilog