文件名称:32bitcpu

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 12.9mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 杨*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

用verilog写的32位CPU源码,通过汇编语言可以实现加减乘除左移右移等运算。并且通过Lookahead算法提高了运算效率,大大节省了运算时间。通过ASC流程可以模拟出其内部电路结构。代码,过程文件,readme在文件夹中-Written by 32-bit CPU verilog source code, assembly language can be achieved through the addition, subtraction and other operations right left. And through the Lookahead algorithm improve the efficiency, significant savings in computing time. ASC process can be simulated by its internal circuit. Code, process documents, readme in the folder
相关搜索: cpu
verilog
32
cpu
32bit
Verilog

(系统自动生成,下载前可以参看下载内容)

下载文件列表

lookahead\cell.rep

.........\code.hex

.........\command.log

.........\compile_bgx.scr

.........\compile_dc.scr

.........\cpu32.conn.rpt

.........\cpu32.cts_trace

.........\cpu32.db

.........\cpu32.geom.rpt

.........\cpu32.sdc

.........\cpu32.v

.........\cpu32.vh

.........\cpu32_test.v

.........\cts.rguide

.........\encounter.cmd

.........\encounter.cmd1

.........\encounter.cmd2

.........\encounter.conf

.........\encounter.cts

.........\encounter.io

.........\encounter.log

.........\encounter.log1

.........\encounter.log2

.........\encounter.log3

.........\encounter.tcl

.........\filenames.log

.........\final.dspf

.........\final.gds2

.........\final.v

.........\gds2_encounter.map

.........\gds2_icfb.map

.........\gds2_seultra.map

.........\ipo1.txt

.........\ipo2.txt

.........\magic\AND2X1.ext

.........\.....\AND2X1.mag

.........\.....\AND2X2.ext

.........\.....\AND2X2.mag

.........\.....\AOI21X1.ext

.........\.....\AOI21X1.mag

.........\.....\AOI22X1.ext

.........\.....\AOI22X1.mag

.........\.....\BUFX2.ext

.........\.....\BUFX2.mag

.........\.....\BUFX4.ext

.........\.....\BUFX4.mag

.........\.....\CLKBUF1.mag

.........\.....\CLKBUF2.mag

.........\.....\CLKBUF3.mag

.........\.....\cpu32.al

.........\.....\cpu32.ext

.........\.....\cpu32.mag

.........\.....\cpu32.nodes

.........\.....\cpu32.sim

.........\.....\cpu32_noRC.sim

.........\.....\cpu32_VIA0.ext

.........\.....\cpu32_VIA0.mag

.........\.....\cpu32_VIA1.ext

.........\.....\cpu32_VIA1.mag

.........\.....\DFFNEGX1.mag

.........\.....\DFFPOSX1.ext

.........\.....\DFFPOSX1.mag

.........\.....\DFFSR.mag

.........\.....\FAX1.mag

.........\.....\FILL.ext

.........\.....\FILL.mag

.........\.....\HAX1.mag

.........\.....\INVX1.mag

.........\.....\INVX2.ext

.........\.....\INVX2.mag

.........\.....\INVX4.ext

.........\.....\INVX4.mag

.........\.....\INVX8.ext

.........\.....\INVX8.mag

.........\.....\LATCH.mag

.........\.....\M2_M1.ext

.........\.....\M2_M1.mag

.........\.....\M3_M2.ext

.........\.....\M3_M2.mag

.........\.....\magic.log

.........\.....\MUX2X1.ext

.........\.....\MUX2X1.mag

.........\.....\NAND2X1.ext

.........\.....\NAND2X1.mag

.........\.....\NAND3X1.ext

.........\.....\NAND3X1.mag

.........\.....\NOR2X1.ext

.........\.....\NOR2X1.mag

.........\.....\NOR3X1.mag

.........\.....\OAI21X1.ext

.........\.....\OAI21X1.mag

.........\.....\OAI22X1.ext

.........\.....\OAI22X1.mag

.........\.....\OR2X1.mag

.........\.....\OR2X2.mag

.........\.....\osu_stdcells_pads.mag

.........\.....\PADFC.mag

.........\.....\PADGND.mag

.........\.....\PADINC.mag

.........\.....\PADINOUT.mag

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