文件名称:hw1

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [PDF]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 357kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • vi***
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  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

Using the schematic Design Entry Method, design a logic circuit that has two 2-bit inputs X and Y, a 1-bit input CinOrBin, and a 1-bit control input SubAddn. When the control input SubAddn is ‘0’, the logic circuit behaves as a 2-bit adder ( X + Y + CinOrBin ) with CinOrBin as the carry-in when the control input SubAddn is ‘1’ and the logic circuit behaves as a 2-bit subtracter ( X – Y – CinOrBin ) with CinOrBin as the borrow-in. You must use Half-Adders and Half-Subtracters as building blocks to obtain a structured design. -Using the schematic Design Entry Method, design a logic circuit that has two 2-bit inputs X and Y, a 1-bit input CinOrBin, and a 1-bit control input SubAddn. When the control input SubAddn is ‘0’, the logic circuit behaves as a 2-bit adder ( X + Y + CinOrBin ) with CinOrBin as the carry-in when the control input SubAddn is ‘1’ and the logic circuit behaves as a 2-bit subtracter ( X – Y – CinOrBin ) with CinOrBin as the borrow-in. You must use Half-Adders and Half-Subtracters as building blocks to obtain a structured design.
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下载文件列表

hw1\addsub.asm.rpt

...\addsub.bdf

...\addsub.done

...\addsub.fit.rpt

...\addsub.fit.summary

...\addsub.flow.rpt

...\addsub.map.rpt

...\addsub.map.summary

...\addsub.pin

...\addsub.pof

...\addsub.qpf

...\addsub.qsf

...\addsub.qws

...\addsub.sim.rpt

...\addsub.sof

...\addsub.tan.rpt

...\addsub.tan.summary

...\addsub.vwf

...\db\addsub.asm.qmsg

...\..\addsub.asm_labs.ddb

...\..\addsub.cbx.xml

...\..\addsub.cmp.bpm

...\..\addsub.cmp.cdb

...\..\addsub.cmp.ecobp

...\..\addsub.cmp.hdb

...\..\addsub.cmp.kpt

...\..\addsub.cmp.logdb

...\..\addsub.cmp.rdb

...\..\addsub.cmp.tdb

...\..\addsub.cmp0.ddb

...\..\addsub.cmp_merge.kpt

...\..\addsub.db_info

...\..\addsub.eco.cdb

...\..\addsub.eds_overflow

...\..\addsub.fit.qmsg

...\..\addsub.fnsim.cdb

...\..\addsub.fnsim.hdb

...\..\addsub.fnsim.qmsg

...\..\addsub.hier_info

...\..\addsub.hif

...\..\addsub.map.bpm

...\..\addsub.map.cdb

...\..\addsub.map.ecobp

...\..\addsub.map.hdb

...\..\addsub.map.kpt

...\..\addsub.map.logdb

...\..\addsub.map.qmsg

...\..\addsub.map_bb.cdb

...\..\addsub.map_bb.hdb

...\..\addsub.map_bb.hdbx

...\..\addsub.map_bb.logdb

...\..\addsub.pre_map.cdb

...\..\addsub.pre_map.hdb

...\..\addsub.psp

...\..\addsub.rtlv.hdb

...\..\addsub.rtlv_sg.cdb

...\..\addsub.rtlv_sg_swap.cdb

...\..\addsub.sgdiff.cdb

...\..\addsub.sgdiff.hdb

...\..\addsub.sim.hdb

...\..\addsub.sim.qmsg

...\..\addsub.sim.rdb

...\..\addsub.simfam

...\..\addsub.sim_ori.vwf

...\..\addsub.sld_design_entry.sci

...\..\addsub.sld_design_entry_dsc.sci

...\..\addsub.syn_hier_info

...\..\addsub.tan.qmsg

...\..\addsub.tis_db_list.ddb

...\..\addsub.tmw_info

...\..\mux_lmc.tdf

...\..\prev_cmp_addsub.asm.qmsg

...\..\prev_cmp_addsub.fit.qmsg

...\..\prev_cmp_addsub.map.qmsg

...\..\prev_cmp_addsub.qmsg

...\..\prev_cmp_addsub.sim.qmsg

...\..\prev_cmp_addsub.tan.qmsg

...\..\wed.wsf

...\halfadder.bdf

...\halfadder.bsf

...\halfsub.bdf

...\halfsub.bsf

...\incremental_db\compiled_partitions\addsub.root_partition.cmp.atm

...\..............\...................\addsub.root_partition.cmp.dfp

...\..............\...................\addsub.root_partition.cmp.hdbx

...\..............\...................\addsub.root_partition.cmp.kpt

...\..............\...................\addsub.root_partition.cmp.logdb

...\..............\...................\addsub.root_partition.cmp.rcf

...\..............\...................\addsub.root_partition.map.atm

...\..............\...................\addsub.root_partition.map.dpi

...\..............\...................\addsub.root_partition.map.hdbx

...\..............\...................\addsub.root_partition.map.kpt

...\..............\README

...\printout\addsub functional waveform.pdf

...\........\addsub timing waveform.pdf

...\........\addsub.pdf

...\........\Fitter Resource Usage Summary.pdf

...\........\halfadder.pdf

...\........\halfsub.pdf

...\........\manual verification.xlsx

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