文件名称:logic_analysis

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 4.12mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • MR***
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

逻辑分析仪是一种类似于示波器的波形测试设备,它可以监测硬件电路工作时的逻辑电

平(高或低),存储后用图形的方式直观地表达出来,主要是方便用户在数字电路的调试中

观察输出的逻辑电平值。逻辑分析仪是电路开发中不可缺少的设备,通过它,可以迅速地定

位错误,解决问题,达到事半功倍的效果。如图 6.1 所示,一个逻辑分析的基本功能架构主

要包括数据采样、触发控制、数据存储和现实控制四大部分。 -Logic analyzer is an oscilloscope waveform similar test equipment, which can monitor the hardware logic circuit work

Level (high or low), storage for later use intuitive graphical way to express, mainly to facilitate the user in the digital circuit debugging

Observed value of the output logic level. Circuit logic analyzer is an indispensable device development, through it, you can quickly set

Bit errors, solve problems and achieve a multiplier effect. As shown in Figure 6.1, the basic functions of a logical analysis of the primary structure

To include data sampling, trigger control, data storage and real control of four major parts.
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下载文件列表

logic_analysis\logic_analysis\char_rom.bsf

..............\..............\char_rom.qip

..............\..............\char_rom.v

..............\..............\char_rom_bb.v

..............\..............\char_rom_data.mif

..............\..............\char_rom_data.rar

..............\..............\char_rom_inst.v

..............\..............\char_rom_wave0.jpg

..............\..............\char_rom_waveforms.html

..............\..............\Ch_rom.qip

..............\..............\db\altsyncram_0e71.tdf

..............\..............\..\altsyncram_5m31.tdf

..............\..............\..\altsyncram_dg61.tdf

..............\..............\..\altsyncram_fc61.tdf

..............\..............\..\altsyncram_hd51.tdf

..............\..............\..\altsyncram_lp51.tdf

..............\..............\..\altsyncram_n0a1.tdf

..............\..............\..\altsyncram_op51.tdf

..............\..............\..\altsyncram_ql51.tdf

..............\..............\..\altsyncram_u0a1.tdf

..............\..............\..\cntr_0df.tdf

..............\..............\..\logic_analysis.cbx.xml

..............\..............\..\logic_analysis.cmp.hdb

..............\..............\..\logic_analysis.cmp.rdb

..............\..............\..\logic_analysis.cmp_merge.kpt

..............\..............\..\logic_analysis.db_info

..............\..............\..\logic_analysis.eco.cdb

..............\..............\..\logic_analysis.eda.qmsg

..............\..............\..\logic_analysis.hier_info

..............\..............\..\logic_analysis.hif

..............\..............\..\logic_analysis.lpc.html

..............\..............\..\logic_analysis.lpc.rdb

..............\..............\..\logic_analysis.lpc.txt

..............\..............\..\logic_analysis.map.bpm

..............\..............\..\logic_analysis.map.cdb

..............\..............\..\logic_analysis.map.ecobp

..............\..............\..\logic_analysis.map.hdb

..............\..............\..\logic_analysis.map.kpt

..............\..............\..\logic_analysis.map.logdb

..............\..............\..\logic_analysis.map.qmsg

..............\..............\..\logic_analysis.map_bb.cdb

..............\..............\..\logic_analysis.map_bb.hdb

..............\..............\..\logic_analysis.map_bb.logdb

..............\..............\..\logic_analysis.pre_map.cdb

..............\..............\..\logic_analysis.pre_map.hdb

..............\..............\..\logic_analysis.rtlv.hdb

..............\..............\..\logic_analysis.rtlv_sg.cdb

..............\..............\..\logic_analysis.rtlv_sg_swap.cdb

..............\..............\..\logic_analysis.sgdiff.cdb

..............\..............\..\logic_analysis.sgdiff.hdb

..............\..............\..\logic_analysis.sld_design_entry.sci

..............\..............\..\logic_analysis.sld_design_entry_dsc.sci

..............\..............\..\logic_analysis.smart_action.txt

..............\..............\..\logic_analysis.syn_hier_info

..............\..............\..\logic_analysis.tis_db_list.ddb

..............\..............\..\logic_analysis.tmw_info

..............\..............\..\logic_analysis_global_asgn_op.abo

..............\..............\..\logic_util_heursitic.dat

..............\..............\..\prev_cmp_logic_analysis.asm.qmsg

..............\..............\..\prev_cmp_logic_analysis.eda.qmsg

..............\..............\..\prev_cmp_logic_analysis.fit.qmsg

..............\..............\..\prev_cmp_logic_analysis.map.qmsg

..............\..............\..\prev_cmp_logic_analysis.qmsg

..............\..............\..\prev_cmp_logic_analysis.sta.qmsg

..............\..............\..\prev_cmp_logic_analysis.tan.qmsg

..............\..............\..\shift_taps_csr.tdf

..............\..............\..\shift_taps_qsr.tdf

..............\..............\incremental_db\compiled_partitions\logic_analysis.root_partition.cmp.atm

..............\..............\..............\...................\logic_analysis.root_partition.cmp.cdb

..............\..............\..............\...................\logic_analysis.root_partition.cmp.dfp

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