文件名称:source
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FPGA中实现I2C接口的一个IP核，包含verilog及VHDL代码。方便迅速理解和开发I2C总线接口。-FPGA to implement an I2C interface IP core that contains verilog and VHDL code. Facilitate rapid understanding and development of I2C bus interface.
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下载文件列表
source\verilog\i2c_master_bit_ctrl.v
......\.......\i2c_master_byte_ctrl.v
......\.......\i2c_master_defines.v
......\.......\i2c_master_registers.v
......\.......\i2c_master_wb_top.v
......\.......\timescale.v
......\.hdl\i2c_master_bit_ctrl.vhd
......\....\i2c_master_byte_ctrl.vhd
......\....\i2c_master_registers.vhd
......\....\i2c_master_wb_top.vhd
......\verilog
......\vhdl
source
......\.......\i2c_master_byte_ctrl.v
......\.......\i2c_master_defines.v
......\.......\i2c_master_registers.v
......\.......\i2c_master_wb_top.v
......\.......\timescale.v
......\.hdl\i2c_master_bit_ctrl.vhd
......\....\i2c_master_byte_ctrl.vhd
......\....\i2c_master_registers.vhd
......\....\i2c_master_wb_top.vhd
......\verilog
......\vhdl
source