文件名称:DDRSDRAM_controller
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ddr sdram控制器，lattice器件的参考设计，比较详细-ddr sdram controller, lattice components of the reference design, very detailed
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下载文件列表
DDR RAM控制器的VHDL源码\使用说明请参看右侧注释====〉〉.txt
.......................\rd1020_DDR SDRAM Controller\DDR SDRAM Controller.htm
.......................\...........................\rd1020.pdf
.......................\...........................\DDR SDRAM Controller.files\arrow.gif
.......................\...........................\..........................\arrow1.gif
.......................\...........................\..........................\ddr_controller.gif
.......................\...........................\..........................\diskette.gif
.......................\...........................\..........................\external.css
.......................\...........................\..........................\footer.gif
.......................\...........................\..........................\go.gif
.......................\...........................\..........................\header.gif
.......................\...........................\..........................\make_agent_emb.jpg
.......................\...........................\..........................\pdfmid.gif
.......................\...........................\..........................\ref_design_logo.gif
.......................\...........................\..........................\spacer.gif
.......................\...........................\..........................\Thumbs.db
.......................\...........................\source\ddr_ctrl.v
.......................\...........................\......\ddr_data.v
.......................\...........................\......\ddr_par.v
.......................\...........................\......\ddr_pll_orca.v
.......................\...........................\......\ddr_pll_orca_sp.v
.......................\...........................\......\ddr_sig.v
.......................\...........................\......\ddr_top.v
.......................\...........................\......\transcript
.......................\...........................\testbench\ddr_tb.v
.......................\...........................\.........\stimulus.v
.......................\...........................\DDR SDRAM Controller.files
.......................\...........................\source
.......................\...........................\testbench
.......................\rd1020_DDR SDRAM Controller
DDR RAM控制器的VHDL源码
.......................\rd1020_DDR SDRAM Controller\DDR SDRAM Controller.htm
.......................\...........................\rd1020.pdf
.......................\...........................\DDR SDRAM Controller.files\arrow.gif
.......................\...........................\..........................\arrow1.gif
.......................\...........................\..........................\ddr_controller.gif
.......................\...........................\..........................\diskette.gif
.......................\...........................\..........................\external.css
.......................\...........................\..........................\footer.gif
.......................\...........................\..........................\go.gif
.......................\...........................\..........................\header.gif
.......................\...........................\..........................\make_agent_emb.jpg
.......................\...........................\..........................\pdfmid.gif
.......................\...........................\..........................\ref_design_logo.gif
.......................\...........................\..........................\spacer.gif
.......................\...........................\..........................\Thumbs.db
.......................\...........................\source\ddr_ctrl.v
.......................\...........................\......\ddr_data.v
.......................\...........................\......\ddr_par.v
.......................\...........................\......\ddr_pll_orca.v
.......................\...........................\......\ddr_pll_orca_sp.v
.......................\...........................\......\ddr_sig.v
.......................\...........................\......\ddr_top.v
.......................\...........................\......\transcript
.......................\...........................\testbench\ddr_tb.v
.......................\...........................\.........\stimulus.v
.......................\...........................\DDR SDRAM Controller.files
.......................\...........................\source
.......................\...........................\testbench
.......................\rd1020_DDR SDRAM Controller
DDR RAM控制器的VHDL源码