在Verilog中有两种类型的赋值语句：连续赋值和过程赋值。赋值表达式由三个部分组成：左值、赋值运算符（=或<=）和右值。右值可以是任何类型的数据，包括net型和register型；但对连续赋值，左值必须是net类型的数据；而过程赋值，左值必须是register类型的数据。下面将作详细描述-There are two types in the Verilog assignment statement: continuous assignment and process assignment. Assignment expression consists of three parts: the left value, the assignment operator (= or < =) and the right values. Right values can be any type of data, including net type and register type　but continuous assignment, the left value must be a net type of data　the process of assignment, the left value must be a register type of data. Described in detail below