文件名称:HALF-ADDER-VHDL
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用硬件描述语言编写的8位全加器代码，很实用通过对代码的编译和波形检测显示出此设计也是完全符合要求的，并且和设计的电路图一样，也达到相同的效果。-Using hardware descr iption language preparation 8 bits QuanJia implement code, is very practical through the code compiler and waveform test shows the design is fully meet the requirements, and design of the circuit diagram, as also achieve the same effect.
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HALF ADDER VHDL
...............\半加器（VHDL）.txt
...............\半加器（VHDL）.txt