文件名称:ADCODE

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [VHDL] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 10.67mb
  • 下载次数:
  • 0次
  • 提 供 者:
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

用FPGA控制双ADC0809读写,用于双AD热备控制,用verilog实现-FPGA control with dual ADC0809 read and write, hot standby control for double AD, with verilog implementation
(系统自动生成,下载前可以参看下载内容)

下载文件列表

SPICODE

.......\code

.......\quartus

.......\.......\adselfcheck.v

.......\.......\adselfcheck.v.bak

.......\.......\ad_cycle.v

.......\.......\ad_cycle.v.bak

.......\.......\ad_process.v.bak

.......\.......\ad_process0.v

.......\.......\ad_process0.v.bak

.......\.......\ad_process1.v

.......\.......\ad_process1.v.bak

.......\.......\ad_top.v

.......\.......\ad_top.v.bak

.......\.......\db

.......\.......\..\logic_util_heursitic.dat

.......\.......\..\prev_cmp_SPI_Master.asm.qmsg

.......\.......\..\prev_cmp_SPI_Master.eda.qmsg

.......\.......\..\prev_cmp_SPI_Master.fit.qmsg

.......\.......\..\prev_cmp_SPI_Master.map.qmsg

.......\.......\..\prev_cmp_SPI_Master.qmsg

.......\.......\..\prev_cmp_SPI_Master.tan.qmsg

.......\.......\..\SPI_Master.asm.qmsg

.......\.......\..\SPI_Master.asm.rdb

.......\.......\..\SPI_Master.asm_labs.ddb

.......\.......\..\SPI_Master.cbx.xml

.......\.......\..\SPI_Master.cmp.cdb

.......\.......\..\SPI_Master.cmp.hdb

.......\.......\..\SPI_Master.cmp.kpt

.......\.......\..\SPI_Master.cmp.logdb

.......\.......\..\SPI_Master.cmp.rdb

.......\.......\..\SPI_Master.cmp.tdb

.......\.......\..\SPI_Master.cmp0.ddb

.......\.......\..\SPI_Master.db_info

.......\.......\..\SPI_Master.eco.cdb

.......\.......\..\SPI_Master.eda.qmsg

.......\.......\..\SPI_Master.fit.qmsg

.......\.......\..\SPI_Master.hier_info

.......\.......\..\SPI_Master.hif

.......\.......\..\SPI_Master.lpc.html

.......\.......\..\SPI_Master.lpc.rdb

.......\.......\..\SPI_Master.lpc.txt

.......\.......\..\SPI_Master.map.cdb

.......\.......\..\SPI_Master.map.hdb

.......\.......\..\SPI_Master.map.logdb

.......\.......\..\SPI_Master.map.qmsg

.......\.......\..\SPI_Master.pre_map.cdb

.......\.......\..\SPI_Master.pre_map.hdb

.......\.......\..\SPI_Master.rpp.qmsg

.......\.......\..\SPI_Master.rtlv.hdb

.......\.......\..\SPI_Master.rtlv_sg.cdb

.......\.......\..\SPI_Master.rtlv_sg_swap.cdb

.......\.......\..\SPI_Master.sgate.rvd

.......\.......\..\SPI_Master.sgate_sm.rvd

.......\.......\..\SPI_Master.sgdiff.cdb

.......\.......\..\SPI_Master.sgdiff.hdb

.......\.......\..\SPI_Master.sld_design_entry.sci

.......\.......\..\SPI_Master.sld_design_entry_dsc.sci

.......\.......\..\SPI_Master.smart_action.txt

.......\.......\..\SPI_Master.smp_dump.txt

.......\.......\..\SPI_Master.syn_hier_info

.......\.......\..\SPI_Master.tan.qmsg

.......\.......\..\SPI_Master.tis_db_list.ddb

.......\.......\..\SPI_Master.tmw_info

.......\.......\incremental_db

.......\.......\..............\compiled_partitions

.......\.......\..............\...................\SPI_Master.root_partition.map.kpt

.......\.......\..............\README

.......\.......\simulation

.......\.......\..........\modelsim

.......\.......\..........\........\modelsim.ini

.......\.......\..........\........\msim_transcript

.......\.......\..........\........\rtl_work

.......\.......\..........\........\........\adselfcheck

.......\.......\..........\........\........\...........\verilog.prw

.......\.......\..........\........\........\...........\verilog.psm

.......\.......\..........\........\........\...........\_primary.dat

.......\.......\..........\........\........\...........\_primary.dbs

.......\.......\..........\........\........\...........\_primary.vhd

.......\.......\..........\........\........\ad_cycle

.......\.......\..........\........\........\........\verilog.prw

.......\.......\..........\........\........\........\verilog.psm

.......\.......\..........\........\........\........\_primary.dat

.......\.......\..........\........\........\........\_primary.dbs

.......\.......\..........\........\........\........\_primary.vhd

.......\.......\..........\........\........\ad_process0

.......\.......\..........\........\........\...........\verilog.prw

.......\.......\..........\........\........\...........\verilog.psm

.......\.......\..........\........\........\...........\_primary.dat

.......\.......\..........\........\........\...........\_primary.dbs

.......\.......\..........\........\........\...........\_primary.vhd

.......\.......\..........\........\........\ad_process1

..

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