文件名称:verilog_testbench_genetator
介绍说明--下载内容均来自于网络,请自行研究使用
这是一个perl程序
只需要在cmd中运行,参数为你的Verilog名字
功能是:半自动生成Verilog的testbench,提高编码效率-#-----READ ME of verilog_tb_generate.pl----------------------|
# |
#-----copyright(C) Xzmeng 2010-------------------------------|
# |
#Date:2010-12-18 21:55:48------------------------------------|
# |
#Run the pl followed with the verlog file name,such as aaa.v |
#Put the original verilog file(.v) in the current directory. |
#------------------------------------------------------------|
# |
#And you need to gurrantee that there is only one "input" or |
#"output" per line. |
# |
#------------------------------------------------------------|
只需要在cmd中运行,参数为你的Verilog名字
功能是:半自动生成Verilog的testbench,提高编码效率-#-----READ ME of verilog_tb_generate.pl----------------------|
# |
#-----copyright(C) Xzmeng 2010-------------------------------|
# |
#Date:2010-12-18 21:55:48------------------------------------|
# |
#Run the pl followed with the verlog file name,such as aaa.v |
#Put the original verilog file(.v) in the current directory. |
#------------------------------------------------------------|
# |
#And you need to gurrantee that there is only one "input" or |
#"output" per line. |
# |
#------------------------------------------------------------|
(系统自动生成,下载前可以参看下载内容)
下载文件列表
readme for verilog_tb_generate.pl.txt
verilog_tb_generate.pl
verilog_tb_generate.pl