usrp-fpga-mirror

................\usrp2

................\usrp1

................\.git

................\usrp2\vrt

................\.....\udp

................\.....\top

................\.....\timing

................\.....\testbench

................\.....\simple_gemac

................\.....\serdes

................\.....\sdr_lib

................\.....\opencores

................\.....\models

................\.....\fifo

................\.....\extram

................\.....\coregen

................\.....\control_lib

................\.....\boot_cpld

................\....1\toplevel

................\.....\tb

................\.....\sdr_lib

................\.....\rbf

................\.....\models

................\.....\megacells

................\.....\inband_lib

................\.git\logs

................\....\objects

................\....\hooks

................\....\info

................\....\branches

................\....\refs

................\usrp2\top\u2plus

................\.....\...\u2_rev3_iad

................\.....\...\u2_rev3_2rx_iad

................\.....\...\u2_rev3

................\.....\...\tcl

................\.....\...\single_u2_sim

................\.....\...\eth_test

................\.....\simple_gemac\miim

................\.....\.dr_lib\hb

................\.....\opencores\wb_zbt

................\.....\.........\spi_boot

................\.....\.........\spi

................\.....\.........\simple_pic

................\.....\.........\simple_gpio

................\.....\.........\i2c

................\.....\.........\aemb

................\.....\.........\8b10b

................\.....\models\CY7C1356C

................\....1\toplevel\usrp_std

................\.....\........\usrp_multi

................\.....\........\usrp_inband_usb

................\.....\........\sizetest

................\.....\........\mrfm

................\.....\........\include

................\.....\sdr_lib\hb

................\.....\rbf\rev4

................\.....\...\rev2

................\.git\logs\refs

................\....\objects\info

................\....\.......\pack

................\....\refs\remotes

................\....\....\tags

................\....\....\heads

................\usrp2\sdr_lib\hb\hbd_tb

................\.....\opencores\spi_boot\sw

................\.....\.........\........\sim

................\.....\.........\........\rtl

................\.....\.........\........\doc

................\.....\.........\........\bench

................\.....\.........\...\sim

................\.....\.........\...\rtl

................\.....\.........\...\doc

................\.....\.........\...\bench

................\.....\.........\.imple_pic\rtl

................\.....\.........\.......gpio\rtl

................\.....\.........\i2c\software

................\.....\.........\...\sim

................\.....\.........\...\rtl

................\.....\.........\...\doc

................\.....\.........\...\bench

................\.....\.........\aemb\sw

................\.....\.........\....\sim

................\.....\.........\....\rtl

................\.....\.........\....\doc

................\....1\sdr_lib\hb\hbd_tb

................\.git\logs\refs\heads

................\....\refs\remotes\origin

................\usrp2\opencores\spi_boot\sw\misc

................\.....\.........\........\.im\rtl_sim

................\.....\.........\........\rtl\vhdl

................\.....\.........\........\doc\src

................\.....\.........\........\bench\vhdl

................\.....\.........\...\sim\rtl_sim

................\.....\.........\...\rtl\verilog

................\.....\.........\...\doc\src

................\.....\.........\...\bench\verilog

................\.....\.........\i2c\software\include

................\.....\.........\...\.im\i2c_verilog